CT
Senior Design Verification Engineer PCIe
Accepting applicationsChiplogic Technologies · Bengaluru, Karnataka, India
Full-Time Mid_senior AIASICC++MentorPCIe
Estimated market salary
₹20-37 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
21h ago
Category
Verification
Experience
Mid_senior
Country
India
Company Description Chiplogic Technologies (Chiplogic) is an IP and product engineering services company founded in 2018, specializing in semiconductor, systems, IoT, and AI/ML solutions. The company delivers high-quality, dependable services across the full semiconductor design lifecycle, from concept to silicon. Chiplogic provides offshore development centers (ODC) and turnkey system solutions, including proof-of-concepts and IoT final system integrations. Its AI/ML offerings are built around the proprietary VISARD™ (Video Synthesis And Real-time Dynamics) framework, enabling advanced video and real-time analytics applications. Team members collaborate on cutting-edge technologies and end-to-end product development for global clients.
Role Description We are looking for an experienced Design Verification Engineer with 8+ years of overall experience and strong hands-on expertise in PCIe verification. The candidate will be responsible for end-to-end verification of complex IP and SoC designs, including verification planning, testbench development, coverage closure, debugging, and protocol compliance.
Key Responsibilities
Own end-to-end verification of PCIe IP, subsystem, and SoC-level designs.
Develop verification plans based on architecture documents and design specifications.
Build and maintain scalable SystemVerilog/UVM verification environments.
Create test scenarios for PCIe features, error handling, power management, resets, and interoperability.
Verify PCIe transaction, data link, and physical-layer functionality.
Develop constrained-random and directed test cases.
Work on PCIe configuration space, enumeration, link training, LTSSM, interrupts, ordering rules, and flow control.
Verify advanced features such as MSI/MSI-X, SR-IOV, ATS, AER, ASPM, and low-power states, as applicable.
Develop assertions, functional coverage, checkers, scoreboards, and reference models.
Perform regression analysis, protocol debugging, and root-cause analysis using simulation waveforms and logs.
Drive functional and code-coverage closure.
Collaborate with RTL designers, architects, firmware teams, and validation engineers.
Mentor junior engineers and provide technical guidance throughout the verification lifecycle.
Participate in verification reviews and ensure timely delivery with high quality.
Required Skills
8+ years of hands-on experience in ASIC/SoC Design Verification.
Strong practical experience in PCIe protocol verification.
Solid understanding of PCIe architecture and protocol layers.
Strong expertise in SystemVerilog, UVM, and constrained-random verification.
Experience with SoC/IP-level testbench development and integration.
Proficiency in assertions, functional coverage, code coverage, and coverage closure.
Strong debugging skills using industry-standard simulation and waveform tools.
Experience with simulators such as VCS, Xcelium, or Questa.
Familiarity with scripting languages such as Python, Perl, Tcl, or Shell.
Strong understanding of verification methodologies and complete verification life cycles.
Excellent analytical, communication, and problem-solving skills.
Preferred Qualifications
Experience with PCIe Gen4, Gen5, or Gen6.
Experience using PCIe Verification IP.
Exposure to C/C++ and embedded software-driven verification.
Experience with formal verification, emulation, or post-silicon validation.
Understanding of AXI, AHB, APB, or other SoC protocols.
Experience leading verification modules or mentoring verification engineers.
Education
Bachelor’s or Master’s degree in Electronics, Electrical Engineering, Computer Science, or a related discipline.
Interested candidates can share their updated resumes at [email protected]
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Role Description We are looking for an experienced Design Verification Engineer with 8+ years of overall experience and strong hands-on expertise in PCIe verification. The candidate will be responsible for end-to-end verification of complex IP and SoC designs, including verification planning, testbench development, coverage closure, debugging, and protocol compliance.
Key Responsibilities
Own end-to-end verification of PCIe IP, subsystem, and SoC-level designs.
Develop verification plans based on architecture documents and design specifications.
Build and maintain scalable SystemVerilog/UVM verification environments.
Create test scenarios for PCIe features, error handling, power management, resets, and interoperability.
Verify PCIe transaction, data link, and physical-layer functionality.
Develop constrained-random and directed test cases.
Work on PCIe configuration space, enumeration, link training, LTSSM, interrupts, ordering rules, and flow control.
Verify advanced features such as MSI/MSI-X, SR-IOV, ATS, AER, ASPM, and low-power states, as applicable.
Develop assertions, functional coverage, checkers, scoreboards, and reference models.
Perform regression analysis, protocol debugging, and root-cause analysis using simulation waveforms and logs.
Drive functional and code-coverage closure.
Collaborate with RTL designers, architects, firmware teams, and validation engineers.
Mentor junior engineers and provide technical guidance throughout the verification lifecycle.
Participate in verification reviews and ensure timely delivery with high quality.
Required Skills
8+ years of hands-on experience in ASIC/SoC Design Verification.
Strong practical experience in PCIe protocol verification.
Solid understanding of PCIe architecture and protocol layers.
Strong expertise in SystemVerilog, UVM, and constrained-random verification.
Experience with SoC/IP-level testbench development and integration.
Proficiency in assertions, functional coverage, code coverage, and coverage closure.
Strong debugging skills using industry-standard simulation and waveform tools.
Experience with simulators such as VCS, Xcelium, or Questa.
Familiarity with scripting languages such as Python, Perl, Tcl, or Shell.
Strong understanding of verification methodologies and complete verification life cycles.
Excellent analytical, communication, and problem-solving skills.
Preferred Qualifications
Experience with PCIe Gen4, Gen5, or Gen6.
Experience using PCIe Verification IP.
Exposure to C/C++ and embedded software-driven verification.
Experience with formal verification, emulation, or post-silicon validation.
Understanding of AXI, AHB, APB, or other SoC protocols.
Experience leading verification modules or mentoring verification engineers.
Education
Bachelor’s or Master’s degree in Electronics, Electrical Engineering, Computer Science, or a related discipline.
Interested candidates can share their updated resumes at [email protected]
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