Senior Design Verification Engineer

Design Verification Engineer
Experience level: 7 to 10 years
Location: Bangalore
Role and Responsibilities:
Domain: AXI, PCIe, UCIe protocol experience is highly preferred
1. Must have experience in developing test benches for IP/Subsystems/SoC.
2. In depth knowledge and hands on experience in the execution of verification of SoC/Sub System/IP DV.
3. Previous experience of independently driving IP DV projects from ability to lead a team by providing technical guidance, as well as be part of execution by debugging and SoC architecture understanding capabilities.
4. Strong hands-on experience with UVM/ System Verilog/ DV signoffs.
5. Must have a strong domain expertise in one or more following areas - AXI/PCIe/UCIe.
6. Experience in Hybrid test benches (SV, System C, Python) and System C based reference model test vectors/stimulus-based verification is desirable.

Interested candidates can share resume to neha.c@thundersoft.com
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