TS
Senior Design Verification Engineer
Accepting applicationsTecquire Solutions · Noida, Uttar Pradesh, India
Full-Time Mid_senior RTLSOCSystemVerilogUVM
Estimated market salary
₹31-55 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
1d ago
Category
Verification
Experience
Mid_senior
Country
India
Immediate joiners only
JOB DESCRIPTION
Location - Noida, Bangalore & Hyderabad
Top 5 Required Skills/Mandatory skills
1. SystemVerilog/UVM testbenches
2. Functional Verification Experience
3. Hands on experience in SOC level test bench and test plan development.
4. Knowledge of Amba Protocols
5. Clearcase Repository/GVIM/Linux Commands
Required Education: BTech/Mtech with Min. 2-8yrs of Exp.
Key Words:
Advanced verification methodology such as SystemVerilog-UVM, coverage development, assertion model development, Power-Aware verification
Roles & Responsibilities:
Required exp of 2 to 8 years
Build and maintain UVM/SystemVerilog-based testbenches.
Functional Verification
Write directed and constrained-random test cases.
Use assertions and functional coverage to validate design behavior.
Debug simulation failures and root-cause issues in RTL or testbench.
Power Aware Verification
Coverage and Assertion Closure
Job Description:
Candidate will be responsible for verification plan definition, DV environment development in SV/UVM, SV/C based test case development, Design verification at RTL level, DV Coverage analysis, Coverage improvement at block and SOC level, System scenario and use case verification, Power and Performance analysis for your blocks in SOC, Gate level verification, Functional test vector development and Silicon bring up debug support.
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JOB DESCRIPTION
Location - Noida, Bangalore & Hyderabad
Top 5 Required Skills/Mandatory skills
1. SystemVerilog/UVM testbenches
2. Functional Verification Experience
3. Hands on experience in SOC level test bench and test plan development.
4. Knowledge of Amba Protocols
5. Clearcase Repository/GVIM/Linux Commands
Required Education: BTech/Mtech with Min. 2-8yrs of Exp.
Key Words:
Advanced verification methodology such as SystemVerilog-UVM, coverage development, assertion model development, Power-Aware verification
Roles & Responsibilities:
Required exp of 2 to 8 years
Build and maintain UVM/SystemVerilog-based testbenches.
Functional Verification
Write directed and constrained-random test cases.
Use assertions and functional coverage to validate design behavior.
Debug simulation failures and root-cause issues in RTL or testbench.
Power Aware Verification
Coverage and Assertion Closure
Job Description:
Candidate will be responsible for verification plan definition, DV environment development in SV/UVM, SV/C based test case development, Design verification at RTL level, DV Coverage analysis, Coverage improvement at block and SOC level, System scenario and use case verification, Power and Performance analysis for your blocks in SOC, Gate level verification, Functional test vector development and Silicon bring up debug support.
Show more Show less