TC
Senior Design Verification Engineer
Accepting applicationsTata Consultancy Services · Hyderabad, Telangana, India
Full-Time Associate DDR4DDR5AXIUVMSystemVerilog
Estimated market salary
₹49-89 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
19h ago
Category
Verification
Experience
Associate
Country
India
Senior Design Verification Engineer:
Exp : 5–10 years’ experience
Location: Hyderabad
You will be responsible for verifying DDR4/5 memory controllers and AXI input interfaces for IP-level designs, ensuring full protocol compliance, error handling, data integrity and performance computation for high-speed DDR interfaces.
Education/Experience
B.E/B.Tech or M.E/M.Tech in Electronics, Electrical, or Computer Engineering.
7–10 years’ experience in SoC or IP-level verification (memory subsystems preferred).
Technical Skills
Strong knowledge of DDR protocol (JEDEC specifications).
Experience with SystemVerilog, UVM, and verification methodology.
Hands-on with simulation tools like Synopsys VCS, Cadence Xcelium, or Mentor Questa.
Good understanding of memory controller architecture and timing parameters (setup/hold, tRCD, tRP, etc.).
Knowledge of AXI protocol and its integration with DDR controller.
Familiarity with assertions (SVA), scoreboarding, and functional coverage.
Familiarity with GLS is a plus.
Key Responsibilities
Develop and maintain SystemVerilog UVM-based verification environments for DDR4/DDR5 memory controller and PHY IP.
Define verification plans, design test benches, and create directed and constrained-random testcases.
Write and debug testcases and sequences for DDR protocol features (read/write operations, refresh, training, power-down modes).
Validate ECC, parity, and command/address/data integrity mechanisms.
Develop and debug scoreboards, assertions (SVA), and checkers for data integrity and protocol correctness.
Integrate AXI, APB VIPs with DDR subsystem.
Perform coverage analysis (code, functional, assertion) to ensure verification completeness.
Debug RTL and simulation failures using waveform analysis (SimVision, Verdi).
Work with design teams to debug RTL and root-cause functional/timing issues in RTL and GLS.
Collaborate with post-silicon and firmware teams for memory bring-up and validation.
Soft Skills
Strong analytical and debugging skills.
Able to deliver tasks independently.
Good documentation and communication ability.
Comfortable collaborating across design, validation, and firmware teams.
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Exp : 5–10 years’ experience
Location: Hyderabad
You will be responsible for verifying DDR4/5 memory controllers and AXI input interfaces for IP-level designs, ensuring full protocol compliance, error handling, data integrity and performance computation for high-speed DDR interfaces.
Education/Experience
B.E/B.Tech or M.E/M.Tech in Electronics, Electrical, or Computer Engineering.
7–10 years’ experience in SoC or IP-level verification (memory subsystems preferred).
Technical Skills
Strong knowledge of DDR protocol (JEDEC specifications).
Experience with SystemVerilog, UVM, and verification methodology.
Hands-on with simulation tools like Synopsys VCS, Cadence Xcelium, or Mentor Questa.
Good understanding of memory controller architecture and timing parameters (setup/hold, tRCD, tRP, etc.).
Knowledge of AXI protocol and its integration with DDR controller.
Familiarity with assertions (SVA), scoreboarding, and functional coverage.
Familiarity with GLS is a plus.
Key Responsibilities
Develop and maintain SystemVerilog UVM-based verification environments for DDR4/DDR5 memory controller and PHY IP.
Define verification plans, design test benches, and create directed and constrained-random testcases.
Write and debug testcases and sequences for DDR protocol features (read/write operations, refresh, training, power-down modes).
Validate ECC, parity, and command/address/data integrity mechanisms.
Develop and debug scoreboards, assertions (SVA), and checkers for data integrity and protocol correctness.
Integrate AXI, APB VIPs with DDR subsystem.
Perform coverage analysis (code, functional, assertion) to ensure verification completeness.
Debug RTL and simulation failures using waveform analysis (SimVision, Verdi).
Work with design teams to debug RTL and root-cause functional/timing issues in RTL and GLS.
Collaborate with post-silicon and firmware teams for memory bring-up and validation.
Soft Skills
Strong analytical and debugging skills.
Able to deliver tasks independently.
Good documentation and communication ability.
Comfortable collaborating across design, validation, and firmware teams.
Show more Show less