ST
Senior Design Verification Engineer
Accepting applicationsSynstack Technologies · Hyderabad, Telangana, India
Full-Time Mid_senior SystemVerilogUVMConstrained-RandomTest Plans
Estimated market salary
₹49-89 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
20h ago
Category
Verification
Experience
Mid_senior
Country
India
Senior Design Verification Engineer | Leading Client
Location: PAN India (Multiple Locations)
Work Model: Hybrid / Flexible
Job Type: Full-time
Notice Period: Immediate Joiners Preferred (Looking for candidates who can join within 0 to 30 days)
What You'll Do
Build block- and SoC-level verification environments
Write test plans, directed tests, and constrained-random stimulus
Debug test failures alongside RTL design engineers
Drive functional and code coverage to meet sign-off criteria
Requirements
Methodology: SystemVerilog (SV) & UVM (Universal Verification Methodology) — Expert Leve
lProtocols: Strong experience in at least one of the following
PCIe (Gen 4 / Gen 5 / Gen 6)
Ethernet (10G to 800G, MAC/PCS layers)
DDR (DDR4/5, LPDDR4/5, Memory Controllers)
Concepts: Constrained-random testing, Assertion-Based Verification (SVA), and Functional Coverage closure.
Tools: Synopsys VCS, Cadence Xcelium, or Siemens Questa, and Verdi (for debugging)
Automation: Scripting with Python, Perl, or Bash
Send your updated CV directly to sst.rec4@synstacktech.com, careers@synstacktech.com
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Location: PAN India (Multiple Locations)
Work Model: Hybrid / Flexible
Job Type: Full-time
Notice Period: Immediate Joiners Preferred (Looking for candidates who can join within 0 to 30 days)
What You'll Do
Build block- and SoC-level verification environments
Write test plans, directed tests, and constrained-random stimulus
Debug test failures alongside RTL design engineers
Drive functional and code coverage to meet sign-off criteria
Requirements
Methodology: SystemVerilog (SV) & UVM (Universal Verification Methodology) — Expert Leve
lProtocols: Strong experience in at least one of the following
PCIe (Gen 4 / Gen 5 / Gen 6)
Ethernet (10G to 800G, MAC/PCS layers)
DDR (DDR4/5, LPDDR4/5, Memory Controllers)
Concepts: Constrained-random testing, Assertion-Based Verification (SVA), and Functional Coverage closure.
Tools: Synopsys VCS, Cadence Xcelium, or Siemens Questa, and Verdi (for debugging)
Automation: Scripting with Python, Perl, or Bash
Send your updated CV directly to sst.rec4@synstacktech.com, careers@synstacktech.com
Show more Show less