ST
Senior Design Verification Engineer
Accepting applicationsSynstack Technologies · California, United States
Full-Time Mid_senior RTLSoCUVMVerilog
Posted
3d ago
Category
Verification
Experience
Mid_senior
Country
United States
Design Verification Engineer
San Jose, California
Job Description:
We are seeking DV engineers to verify complex internal IP blocks such as compute engines, accelerators, and custom logic within SoC environments.
Key Responsibilities:
Develop and maintain UVM-based verification environments
Create test plans, testcases, and coverage models
Perform functional verification of RTL designs
Debug RTL and testbench issues
Drive coverage closure (functional + code)
Required Skills:
Strong hands-on with System Verilog and UVM
Experience in block-level verification
Good understanding of digital design fundamentals
Experience with debug tools (Verdi, DVE, etc.)
Good to Have:
Exposure to low-power verification (UPF)
Experience with AMBA protocols (AXI/AHB/APB)
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San Jose, California
Job Description:
We are seeking DV engineers to verify complex internal IP blocks such as compute engines, accelerators, and custom logic within SoC environments.
Key Responsibilities:
Develop and maintain UVM-based verification environments
Create test plans, testcases, and coverage models
Perform functional verification of RTL designs
Debug RTL and testbench issues
Drive coverage closure (functional + code)
Required Skills:
Strong hands-on with System Verilog and UVM
Experience in block-level verification
Good understanding of digital design fundamentals
Experience with debug tools (Verdi, DVE, etc.)
Good to Have:
Exposure to low-power verification (UPF)
Experience with AMBA protocols (AXI/AHB/APB)
Show more Show less