Senior Design Verification Engineer

Senior Design Verification Engineer
Design Verification Lead

San Jose CA, Irvine CA, San Diego CA

Who We Are:
Quest Global delivers world-class end-to-end engineering solutions by leveraging our deep industry knowledge and digital expertise. By bringing together technologies and industries, alongside the contributions of diverse individuals and their areas of expertise, we are able to solve problems better, faster. This multi-dimensional approach enables us to solve the most critical and large-scale challenges across the aerospace & defense, automotive, energy, hi-tech, healthcare, medical devices, rail and semiconductor industries.

We are looking for humble geniuses, who believe that engineering has the potential to make the impossible possible; innovators, who are not only inspired by technology and innovation, but also perpetually driven to design, develop, and test as a trusted partner for Fortune 500 customers. As a team of remarkably diverse engineers, we recognize that what we are really engineering is a brighter future for us all. If you want to contribute to meaningful work and be part of an organization that truly believes when you win, we all win, and when you fail, we all learn, then we’re eager to hear from you.
The achievers and courageous challenge-crushers we seek, have the following characteristics and skills:

Experience Level:
Senior Design Verification Engineer( 6-14 Years of relevant experience required)
Design Verification Lead- (15+ Years of relevant experience required

What will you do:
Develop functional tests based on verification test plan
Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
Debug, root-cause and resolve functional failures in the design, partnering with the design/arch team
Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality

What You Will Bring:
Experience using constrained-random, coverage driven verification or C/C++ verification
Experience in verifying a IP block using standard Design Verification (DV) based techniques
Experience in Electronic Design Automation (EDA) tools and scripting (Python, Tool Command Language (TCL), Perl, Shell) used to build tools and flows for verification environments
Understanding in at least one of the following areas: computer architecture, Central Processing Unit (CPU), Graphics Processing Unit (GPU), networking, interconnects, fabrics or similar designs
Experience debugging fails to the line of RTL, closing out bug fixes, using Verdi or equivalent debug tools
Experience with revision control systems like Mercurial (Hg), Git or SVN
Experience working in a CPU/GPU environment
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