Senior Design Verification Engineer

Responsibilities:
• Work with researchers and architects defining verification plans for each of the different core IP
• Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
• Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality
• Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry

Minimum Qualifications:
8+ years ASIC development cycle industry experience
8+ years of hands-on experience in Verilog, SystemVerilog, C/C++ based verification and UVM methodology
Strong experience with UVM based verification, setting up co-simulation environments with ARM CPU models
5+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies
Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments
Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle

Preferred Qualifications:
• Experience in development of UVM based verification environments from scratch
• Experience with low power design
• Master's degree in Computer Science, Computer Engineering, or a related field
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