LT

Senior Design Verification Engineer

Accepting applications

L&T Technology Services · San Jose, CA

Full-Time Mid_senior RTLSoCSystemVerilogUVM
Posted
20h ago
Category
Verification
Experience
Mid_senior
Country
United States
Job Description:

We are seeking DV engineers to verify complex internal IP blocks such as compute engines, accelerators, and custom logic within SoC environments.

Key Responsibilities:

Develop and maintain UVM-based verification environments
Create test plans, testcases, and coverage models
Perform functional verification of RTL designs
Debug RTL and testbench issues
Drive coverage closure (functional + code)

Required Skills:

Strong hands-on with SystemVerilog and UVM
Experience in block-level verification
Good understanding of digital design fundamentals
Experience with debug tools (Verdi, DVE, etc.)

Good to Have:

Exposure to low-power verification (UPF)
Experience with AMBA protocols (AXI/AHB/APB)

The expected salary range for this position is between $140K - $200K annually. The actual salary may vary based upon several factors including, but not limited to, relevant skills/experience, time in role, base salary of internal peers, prior performance, business line, and geographic/office location.

Paid Leave, Health Insurance, Group life Insurance, Disability, 401(K)
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