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Senior Design Verification Engineer
Accepting applicationsHPR (Hyannis Port Research) · Needham Heights, MA
Full-Time Mid_senior ASICDDREthernetFPGAPCIe
Posted
11 May
Category
Verification
Experience
Mid_senior
Country
United States
HPR is a leading provider of high-performance and ultra-low latency electronic trading and capital markets infrastructure solutions offered as a managed service. Our cutting-edge technology is used by tier-1 financial institutions to monitor and execute trades rapidly and efficiently. As we continue to innovate and grow, we’re searching for a forward-thinking Senior Design Verification Engineer to help us build the future of capital markets infrastructure.
As a Senior Design Verification Engineer at HPR, you will:
Verify and maintain high-performance FPGA compute and networking systems used in electronic trading
Own the verification process from specification, test planning, and testbench development through execution and coverage closure
Partner with design engineers to review and execute comprehensive test plans
Create and maintain reusable verification components and testbenches written in SystemVerilog
Lead and mentor junior engineers, promoting our culture of continuous learning and collaboration
Contribute to improving our verification processes, tools, and methodologies
Required Qualifications
BS/MS in Computer Engineering, Electrical Engineering, Computer Science, or related
5+ years of experience in design verification for FPGAs or ASICs
Proficiency in SystemVerilog for verification
Familiarity with advanced verification methods, including constrained randomization, functional coverage, and assertion-based checking
Experience with industry-standard simulation and debugging tools (e.g., VCS, Verdi)
Comfortable working in a Linux environment
Strong problem solving, debugging, and communication skills
Desired Qualifications
Deep understanding of computer architecture and digital design concepts
In-depth knowledge of networking protocols (IP, TCP, UDP)
Experience verifying designs with high-speed interfaces (PCIe, Ethernet, and/or DDR)
Familiarity with C programming and scripting in Python and/or Perl
This position requires being on-site at our office in Needham, MA full-time (5 days per week)
HPR does not currently provide employment sponsorship
Show more Show less
As a Senior Design Verification Engineer at HPR, you will:
Verify and maintain high-performance FPGA compute and networking systems used in electronic trading
Own the verification process from specification, test planning, and testbench development through execution and coverage closure
Partner with design engineers to review and execute comprehensive test plans
Create and maintain reusable verification components and testbenches written in SystemVerilog
Lead and mentor junior engineers, promoting our culture of continuous learning and collaboration
Contribute to improving our verification processes, tools, and methodologies
Required Qualifications
BS/MS in Computer Engineering, Electrical Engineering, Computer Science, or related
5+ years of experience in design verification for FPGAs or ASICs
Proficiency in SystemVerilog for verification
Familiarity with advanced verification methods, including constrained randomization, functional coverage, and assertion-based checking
Experience with industry-standard simulation and debugging tools (e.g., VCS, Verdi)
Comfortable working in a Linux environment
Strong problem solving, debugging, and communication skills
Desired Qualifications
Deep understanding of computer architecture and digital design concepts
In-depth knowledge of networking protocols (IP, TCP, UDP)
Experience verifying designs with high-speed interfaces (PCIe, Ethernet, and/or DDR)
Familiarity with C programming and scripting in Python and/or Perl
This position requires being on-site at our office in Needham, MA full-time (5 days per week)
HPR does not currently provide employment sponsorship
Show more Show less
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