Senior Design Verification Engineer

Job Description:
12+ years of Design Verification experience.
Good hands on knowledge of SV-UVM
Experience in leading team
Experience in building environment, verification plan, test plan
Experience in building re-usable verification environment for SS, SOC
Experience with integrating third party VIP
Python script expertise
Use of Source Control like git or equivalent
Hands on exp of at least on high speed protocol UCIe/PCIe5+/LPDDR5+/Ethernet200G+
GLS exp
Arm Core/C-Base exp
Emulation exp plus
Multiple high speed protocol exp plus.
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