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Senior Design Verification Engineer
Accepting applicationseInfochips (An Arrow Company) · Hyderabad, Telangana, India
Full-Time Associate CadenceEthernetPerlPythonSOC
Estimated market salary
₹49-89 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
2d ago
Category
Verification
Experience
Associate
Country
India
Job Responsibilities
Coding of testcase for SoC using SystemVerilog (UVM) & C
SoC Level verification is a must.
AMBA bus protocol like AHB, AXI is a must.
Generate Verification Plan from the Specifications using vManager.
Determine Coverage and design completeness requirements.
Generate random-constraint tests to meet coverage requirements.
Create Assertions, cover-groups, checkers, monitors and automatic reporting.
Set-up and run regression, analyze/debug the failure and file JIRA.
Job Requirements
BSEE (MSEE pref.) or equivalent with 5 to 9 years professional industry experience in Digital multi core SoC verification.
Experience in digital Verification.
AUTOMOTIVE SOC is plus – IP like Ethernet, CAN, LIN and MRAM and so on.
UVM testbench creation, writing and implementation is a plus.
Proficient developing scripts (Shell, Perl, Python etc.), and Cadence SKILL language is plus
Must be able to work independently with limited supervision and work closely with team.
Work from office.
Show more Show less
Coding of testcase for SoC using SystemVerilog (UVM) & C
SoC Level verification is a must.
AMBA bus protocol like AHB, AXI is a must.
Generate Verification Plan from the Specifications using vManager.
Determine Coverage and design completeness requirements.
Generate random-constraint tests to meet coverage requirements.
Create Assertions, cover-groups, checkers, monitors and automatic reporting.
Set-up and run regression, analyze/debug the failure and file JIRA.
Job Requirements
BSEE (MSEE pref.) or equivalent with 5 to 9 years professional industry experience in Digital multi core SoC verification.
Experience in digital Verification.
AUTOMOTIVE SOC is plus – IP like Ethernet, CAN, LIN and MRAM and so on.
UVM testbench creation, writing and implementation is a plus.
Proficient developing scripts (Shell, Perl, Python etc.), and Cadence SKILL language is plus
Must be able to work independently with limited supervision and work closely with team.
Work from office.
Show more Show less