Senior Design Verification Engineer

What will you do:
Own block-level RTL verification across our AI accelerator ASIC.
Build testbenches, drive coverage closure, and use AI-assisted tool flows to accelerate verification timelines.

What we’re looking for:
Exceptional abilities in SystemVerilog, UVM, constrained-random verification, and coverage-driven methodology
7+ years verifying complex digital designs at the block or sub-system level
Hands-on with industry-standard simulators (VCS, Xcelium, Riviera, or equivalent) and waveform tools (Verdi, SimVision, or equivalent)
Demonstrated ability to debug RTL / testbench mismatches and drive coverage to target
(Optional) SVA assertion writing, formal methods, RISC-V, emulation, or processor / accelerator verification

Compensation
Base salary: $200k – $350k USD per year, depending on experience and qualifications. Final offers depend on level, location, and skills relevant to the role.
Additional compensation: equity grant per company guidelines; medical / dental / vision; 401(k); standard PTO. Discussed in detail during the interview.

Visa sponsorship
DensityAI sponsors qualified and exceptional candidates for employment-based visas. Work authorization is required at start.

Export controls
Aspects of this role may involve access to information subject to U.S. export controls (EAR/ITAR). We may discuss licensing or scope adjustments during the interview.

Equal Opportunity
DensityAI is an Equal Opportunity Employer. We do not discriminate on the basis of race, color, religious creed, national origin, ancestry, physical or mental disability, medical condition, genetic information, marital status, sex, gender, gender identity, gender expression, age (40+), sexual orientation, military or veteran status, pregnancy, or any other status protected by law. We comply with the California CROWN Act and provide reasonable accommodations on request.
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