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Senior Design Verification Engineer
Accepting applicationsCiliconchip · Bengaluru, Karnataka, India
Full-Time Mid_senior DDREthernetPCIePerlPython
Estimated market salary
₹24-44 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
2d ago
Category
Verification
Experience
Mid_senior
Country
India
Key Requirements:
Methodologies: Strong hands-on UVM / OVM and SystemVerilog (Constrained-Random Verification)
Assertions & Coverage: SystemVerilog Assertions (SVA) & Functional Coverage modeling
Protocols (Any): PCIe, USB, DDR, or Ethernet
EDA Tools: Xcelium, VCS, or Questa
Debug Tools: Verdi or SimVision
Scripting: Python, Perl, or TCL
What You'll Do:
Lead IP/subsystem verification, build UVM environments (monitors, scoreboards, drivers), track coverage closure, run regressions, and mentor junior engineers.
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Methodologies: Strong hands-on UVM / OVM and SystemVerilog (Constrained-Random Verification)
Assertions & Coverage: SystemVerilog Assertions (SVA) & Functional Coverage modeling
Protocols (Any): PCIe, USB, DDR, or Ethernet
EDA Tools: Xcelium, VCS, or Questa
Debug Tools: Verdi or SimVision
Scripting: Python, Perl, or TCL
What You'll Do:
Lead IP/subsystem verification, build UVM environments (monitors, scoreboards, drivers), track coverage closure, run regressions, and mentor junior engineers.
Show more Show less