Senior Design Verification Engineer

Senior Design Verification Engineer – (Austin, TX/Bay Area )
We are hiring W2 candidates only

Location: Austin, TX (Onsite)
Experience: 8+ years
Role: Senior Design Verification Engineer
Key Responsibilities:
Develop and execute verification plans for complex SoC/IP designs.
Build UVM/SystemVerilog-based testbenches and verification environments.
Create directed and constrained-random test cases.
Debug RTL and verification issues, perform root cause analysis.
Develop assertions (SVA), functional coverage, and coverage closure.
Collaborate with RTL designers, architects, and cross-functional teams to ensure first-pass silicon success.

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