Senior Design Verification Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

The Role

The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s wired networking IP, resulting in no bugs in the final design.

The Person

You have a passion for modern, complex architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites and time zones. You have strong analytical and problem‑solving skills and are willing to learn and ready to take on problems.

Key Responsibilities

Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
Estimate the time required to write the new feature tests and any required changes to the test environment
Build the directed and random verification tests
Debug test failures to determine the root cause and work with RTL and firmware engineers to resolve design defects and correct any test issues
Review functional and code coverage metrics and modify or add tests or constrain random tests to meet the coverage requirements


Preferred Experience

Proficient in IP level ASIC verification
Proficient in debugging RTL code using simulation tools
Expert in UVM concepts and SystemVerilog language
Proficient in using UVM testbenches and working in Linux and Windows environments
Experienced in developing UVM‑based verification frameworks and testbenches, processes, and flows
Comfortable automating workflows in a distributed compute environment
Exposure to simulation profile, efficiency improvement, acceleration, and formal verification
Scripting language experience: Perl, Python, Makefile, shell
Exposure to leadership or mentorship
Prior exposure to networking protocols such as Ethernet, UAL, LLR, and CBFC
Experienced in using AI tools


Academic Credentials

Bachelor’s or Master’s degree in Computer Engineering, Electrical Engineering, or Computer Science preferred


Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.

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