AD
Senior Design Verification Engineer
Accepting applicationsACL Digital · Hyderabad, Telangana, India
Full-Time Mid_senior ASICC++SystemVerilog
Estimated market salary
₹11-21 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
3d ago
Category
Verification
Experience
Mid_senior
Country
India
🚀 We are Hiring: Design Verification Engineers (CPU/GPU IP & ASIC) 🚀
ACL Digital is looking for DV Engineers with 2–4 years of experience to drive functional verification for complex CPU/GPU ASICs and IP cores in Hyderabad! If you have strong hands-on experience in C/C++, SystemVerilog, DPI/PLI, and advanced debugging using Verdi, VCS, GDB, or Valgrind, we want to hear from you. You’ll be responsible for developing constrained-random/directed test plans, assertion-based verification, and executing simulation runs under aggressive, high-performance timelines. Immediate joiners or candidates with a 0–30 day notice period are preferred.
📩 Interested? Apply now: Send your resume to janagaradha.n@acldigital.com
Show more Show less
ACL Digital is looking for DV Engineers with 2–4 years of experience to drive functional verification for complex CPU/GPU ASICs and IP cores in Hyderabad! If you have strong hands-on experience in C/C++, SystemVerilog, DPI/PLI, and advanced debugging using Verdi, VCS, GDB, or Valgrind, we want to hear from you. You’ll be responsible for developing constrained-random/directed test plans, assertion-based verification, and executing simulation runs under aggressive, high-performance timelines. Immediate joiners or candidates with a 0–30 day notice period are preferred.
📩 Interested? Apply now: Send your resume to janagaradha.n@acldigital.com
Show more Show less