AT

Senior Design Verification Engineer

Accepting applications

Acceler8 Talent · Mountain View, CA

Full-Time Mid_senior AIDDRPCIePythonRTL
Posted
21 Apr
Category
Verification
Experience
Mid_senior
Country
United States
Acceler8 Talent is partnered with an early-stage company to hire a Design Verification Engineer.


The team is developing advanced AI-focused compute platforms, with innovation spanning from silicon design through system-level integration. Their goal is to build highly optimized infrastructure for next-generation AI workloads.


This position focuses on developing and owning verification efforts for a new class of AI silicon. Rather than maintaining existing environments, the role emphasizes building verification infrastructure and methodology from the ground up. The engineer will work across block and SoC levels, collaborating closely with architecture and design teams.


Key Responsibilities
Develop scalable verification environments using SystemVerilog and UVM, starting from initial setup through full deployment
Define and implement test strategies, including constrained-random approaches and functional coverage models
Debug complex issues spanning RTL components and full-system interactions
Establish verification workflows, regression strategies, and supporting automation frameworks
Partner closely with RTL and architecture teams to ensure design correctness and coverage
Contribute to the development and standardization of verification methodologies across the organization


Qualifications
Strong proficiency in SystemVerilog and UVM
Experience building verification environments from the ground up
Solid debugging skills across both RTL and system-level behavior
Understanding of modern SoC design, including interconnects and integration challenges
Experience with scripting languages such as Python, TCL, or similar
Background in high-performance compute systems (e.g., CPUs, GPUs, or AI accelerators)
Familiarity with emulation platforms or post-silicon validation
Exposure to high-speed interfaces such as PCIe, DDR, or similar technologies
Experience working in startup or rapidly evolving environments


Leveling & Expectations
*Openings available at senior through principal levels, depending on experience and scope
Expected to take ownership of verification areas and drive them independently
Comfortable working with limited structure and high levels of autonomy
Focused on building scalable systems and infrastructure, not just individual tests
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