H
Senior Design Engineer
Accepting applicationsHCLTech · Bengaluru, Karnataka, India
Full-Time Mid_senior SystemVerilogUVMTestbenchFunctionalVerificationCoverage
Estimated market salary
₹10-18 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
3d ago
Category
Verification
Experience
Mid_senior
Country
India
Job Summary:
We are seeking a highly skilled Design Verification Engineer (DV) to join our growing team and play a vital role in ensuring the quality and functionality of our advanced ASICs and SoCs. This position requires a strong foundation in verification methodologies and the ability to handle complex verification tasks. You will be instrumental in developing robust verification plans and environments to guarantee the success of our next-generation integrated circuits.
Responsibilities
:Develop and implement comprehensive verification plans utilizing industry-leading methodologies (UVM, Formal Verification
)Design and create high-quality verification environments (testbenches) to achieve exceptional code coverag
eUtilize advanced verification tools (simulators, formal verification tools) to thoroughly verify RTL functionalit
yDebug and analyze verification failures with a keen eye to identify and resolve the root cause of design issue
sCollaborate effectively with RTL design engineers to ensure efficient bug resolution and verification plan adherenc
eLead and mentor junior DV engineers within the team, fostering a collaborative and knowledge-sharing environmen
tParticipate in code reviews and champion best practices for verification code qualit
yStay current with the latest advancements in verification tools and methodologie
s
Qualification
s:Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plu
s)7-10 years of solid experience in Design Verification for ASICs or So
CsIn-depth knowledge of digital design principles (combinational logic, sequential logic, finite state machine
s)Proven ability to develop, debug, and optimize complex verification environmen
tsExpertise in Verilog or VHDL with a strong understanding of verification methodologies (UVM, Forma
l)Extensive experience with simulation tools (ModelSim, Cadence Incisive, Synopsys VCS) and scripting languages (Python, Per
l)Experience with formal verification tools and techniques is a pl
usExcellent analytical and problem-solving skills with a meticulous attention to deta
ilStrong communication, collaboration, and leadership skills to effectively contribute and guide the te
am
Benefi
ts:Competitive salary and benefits package commensurate with experie
nceOpportunity to work on leading-edge technologies and projects with a high imp
actCollaborative and dynamic work environment that fosters continuous learn
ingPotential for professional development and career advancem
ent
Show more Show less
We are seeking a highly skilled Design Verification Engineer (DV) to join our growing team and play a vital role in ensuring the quality and functionality of our advanced ASICs and SoCs. This position requires a strong foundation in verification methodologies and the ability to handle complex verification tasks. You will be instrumental in developing robust verification plans and environments to guarantee the success of our next-generation integrated circuits.
Responsibilities
:Develop and implement comprehensive verification plans utilizing industry-leading methodologies (UVM, Formal Verification
)Design and create high-quality verification environments (testbenches) to achieve exceptional code coverag
eUtilize advanced verification tools (simulators, formal verification tools) to thoroughly verify RTL functionalit
yDebug and analyze verification failures with a keen eye to identify and resolve the root cause of design issue
sCollaborate effectively with RTL design engineers to ensure efficient bug resolution and verification plan adherenc
eLead and mentor junior DV engineers within the team, fostering a collaborative and knowledge-sharing environmen
tParticipate in code reviews and champion best practices for verification code qualit
yStay current with the latest advancements in verification tools and methodologie
s
Qualification
s:Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plu
s)7-10 years of solid experience in Design Verification for ASICs or So
CsIn-depth knowledge of digital design principles (combinational logic, sequential logic, finite state machine
s)Proven ability to develop, debug, and optimize complex verification environmen
tsExpertise in Verilog or VHDL with a strong understanding of verification methodologies (UVM, Forma
l)Extensive experience with simulation tools (ModelSim, Cadence Incisive, Synopsys VCS) and scripting languages (Python, Per
l)Experience with formal verification tools and techniques is a pl
usExcellent analytical and problem-solving skills with a meticulous attention to deta
ilStrong communication, collaboration, and leadership skills to effectively contribute and guide the te
am
Benefi
ts:Competitive salary and benefits package commensurate with experie
nceOpportunity to work on leading-edge technologies and projects with a high imp
actCollaborative and dynamic work environment that fosters continuous learn
ingPotential for professional development and career advancem
ent
Show more Show less