S
Senior CPU Design Verification Engineer
Accepting applicationsSivaltech · San Jose, CA
Full-Time Mid_senior ARMASICRISC-VRTLSoC
Posted
22h ago
Category
Verification
Experience
Mid_senior
Country
United States
CPU Design Verification Engineer
Location: USA
Experience: 5+ years
Key Responsibilities:
Develop and execute verification plans for CPU/processor designs.
Build and maintain SystemVerilog/UVM verification environments.
Develop test cases, checkers, scoreboards, assertions, and functional coverage.
Verify CPU cores, pipelines, caches, memory subsystems, and related interfaces.
Debug RTL and simulation failures and work closely with design engineers.
Drive functional and code coverage closure.
Perform block-level and chip-level verification.
Analyze failures and identify design/verification issues.
Required Skills:
Strong experience in Design Verification / RTL Verification.
Excellent SystemVerilog and UVM experience.
CPU/processor architecture and verification experience.
Experience with SVA (SystemVerilog Assertions).
Functional coverage and code coverage.
Experience with simulation/debug tools such as VCS, Verdi, or similar.
Good understanding of RTL design and digital logic.
Experience with CPU cores, SoC, or semiconductor ASIC verification preferred.
Strong debugging and problem-solving skills.
Preferred:
Experience with RISC-V, ARM, x86, or other CPU architectures and familiarity with cache coherency, pipelines, interrupts, and memory systems.
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Location: USA
Experience: 5+ years
Key Responsibilities:
Develop and execute verification plans for CPU/processor designs.
Build and maintain SystemVerilog/UVM verification environments.
Develop test cases, checkers, scoreboards, assertions, and functional coverage.
Verify CPU cores, pipelines, caches, memory subsystems, and related interfaces.
Debug RTL and simulation failures and work closely with design engineers.
Drive functional and code coverage closure.
Perform block-level and chip-level verification.
Analyze failures and identify design/verification issues.
Required Skills:
Strong experience in Design Verification / RTL Verification.
Excellent SystemVerilog and UVM experience.
CPU/processor architecture and verification experience.
Experience with SVA (SystemVerilog Assertions).
Functional coverage and code coverage.
Experience with simulation/debug tools such as VCS, Verdi, or similar.
Good understanding of RTL design and digital logic.
Experience with CPU cores, SoC, or semiconductor ASIC verification preferred.
Strong debugging and problem-solving skills.
Preferred:
Experience with RISC-V, ARM, x86, or other CPU architectures and familiarity with cache coherency, pipelines, interrupts, and memory systems.
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