Senior ASIC Synthesis & STA Engineer

Job Title - Senior ASIC Synthesis + STA Engineer
Job Location- San Jose-CA
Experienced Required - 20+ Years
Job Type - Full Time with Benefits

Job Description -

Accomplished Senior ASIC Synthesis & Timing Engineer with 20+ years of hands-on experience delivering silicon across multiple high-volume consumer electronics tape outs, with deep specialization in full-chip and block-level synthesis, static timing analysis, and end-to-end timing closure using Primetime (PTSI/DMSA) and Design Compiler.
Proven leader in SDC constraints development, UPF-based low-power implementation, and formal equivalence verification (Conformal LEC/Formality), with a track record of building and owning synthesis and STA methodologies from the ground up — not merely executing inherited flows.
Recognized for bridging RTL, IP, library, and physical design teams to resolve integration challenges and enforce RTL quality standards that translate directly into cleaner, faster timing closure.
Hands-on expert in TCL-driven flow automation, timing ECO development, and DMSA-based multi-scenario analysis, with additional depth in power analysis via Redhawk and PTPX across advanced process nodes.
Combines the technical rigor of an MSEE (Purdue, VLSI focus) with the practical judgment earned across Coherent, Apple, Marvell, and Transmeta — bringing both strategic methodology ownership and day-to-day synthesis execution to complex, high-stakes ASIC programs.
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