Senior ASIC RTL Engineer, Silicon

Minimum qualifications:

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
8 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog.
Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques.

Preferred qualifications:

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, or a related field.
Experience with a scripting language like Perl or Python.
Experience with ASIC or FPGA design verification, synthesis, timing/power analysis, and DFT.
Experience in one or more functional areas, such as coherent fabrics (e.g., AMBA CHI/AXI), memory controllers (e.g., LPDDR5, DDR5), or I/O controllers (e.g., PCIe, CXL).
Experience with design sign-off and quality tools (e.g., Lint, CDC, etc.).
Knowledge of memory compression, fabric, coherence, cache, or DRAM.

About The Job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

Perform RTL coding, function/performance simulation debug, and Lint/Clock Domain Crossing (CDC)/Formal Verification (FV)/Unified Power Format (UPF) checks.
Participate in synthesis, timing/power closure, and FPGA/silicon bring-up.
Own and execute the RTL design and micro-architecture for high-performance Fabrics and Network-on-Chip (NoC) subsystems from concept to tape-out.
Write production-quality SystemVerilog code for complex logic including credit-based flow control, asynchronous bridges, and cache coherency controllers.
Debug complex silicon issues and architectural bugs by digging into waveforms and gate-level simulations.


Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .
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