Senior ASIC physical design engineer

Company Description

Eximietas Design is a leading technology consulting and solutions development company specializing in Chip Design, Firmware & Embedded Software, Cloud Computing, Cyber Security, and AI/ML. With an experienced engineering leadership team responsible for over 100+ successful chip tape-outs and numerous software solutions for global tech giants, Eximietas Design is committed to innovation and excellence. We deliver advanced solutions to help organizations excel in the rapidly evolving digital world. The company is ISO 9001 and ISO 27001 certified, with development centers in the United States and India.

Role Description

Are you ready to tape out the next beast 🧌 chip? Join our team and turn complex constraints into clean GDSII.
Too many buffers 🚧 in your life? Come optimize power, area, and performance with a team that values a clean design ⚡

We are hiring top-notch talent in ASIC Physical Design, 10+yrs, to grow with our team. Additional skills preferred: You have good background in SoC level/block timing closure, STA, Power analysis, Physical verification and EM/IR/ESD closure.

This is a full-time hybrid role for a Senior ASIC Physical Design Engineer based in San Jose or San Diego, CA, with flexibility for partial remote work. The incumbent will be responsible for leading ASIC physical design projects, including tasks such as floor planning, partitioning, clock tree synthesis, routing, timing closure, and design rule checking (DRC)/layout versus schematic (LVS) validation. The role also involves collaborating with cross-functional teams, ensuring the design aligns with specifications, and optimizing performance, power, and area parameters.

Qualifications

Strong expertise in Physical Design, including floor planning, implementation, STA timing closure, and verification.
Proficiency in RTL Design and RTL Coding, with experience in Verilog or VHDL.
Proven experience in Logic Design and Formal Verification techniques.
Solid understanding of timing analysis, congestion analysis, and power optimization.
Excellent problem-solving skills, attention to detail, and a high level of technical competence.
Strong communication and interpersonal skills, with the ability to work collaboratively across cross-functional teams.
Master’s or Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, with relevant hands-on experience.
Industry experience with successful ASIC design tape-outs is highly desirable.
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