Senior ASIC Engineer

We are seeking a Physical Design Engineer with a broad, versatile skillset to join a small, high-impact hardware team building performance-critical compute systems. In this role, you will help deliver cutting-edge ASICs on advanced nodes while shaping the physical design methodologies that power them.
This team operates at the intersection of hardware, systems, and performance engineering, building custom compute engines using FPGA and ASIC technologies for latency-sensitive, real-time decision-making systems. The work spans from bespoke datapaths to machine learning accelerators, where microseconds, and often nanoseconds, matter.
You will have end-to-end ownership and the opportunity to directly influence architecture, performance, and design methodology.

What You'll Work On
High-frequency, latency-critical ASICs on advanced process nodes (e.g., 5nm/7nm/16nm)
Custom compute architectures optimized for throughput, determinism, and latency
Systems that combine ASIC + FPGA prototyping and bring-up
Design problems where standard flows are insufficient, requiring creativity and new methodology

Responsibilities
Own physical implementation from RTL handoff through GDSII, including signoff on advanced nodes
Drive and implement DFT strategies, ensuring testability without compromising performance
Partner with architecture and RTL teams on floorplanning, microarchitecture, and physical-aware design decisions
Achieve timing closure across MMMC scenarios, pushing aggressive frequency and latency targets
Optimize designs across power, performance, and area (PPA) with emphasis on performance and latency
Diagnose and resolve complex issues including timing bottlenecks, congestion, IR drop, and EM violations
Build and scale robust, automated physical design flows for fast iteration and high confidence
Develop Python/Tcl-based tooling to improve observability, debugging, and QoR tracking
Influence early-stage design decisions to avoid backend bottlenecks before they occur

Qualifications
5+ years of professional working experience required
Proven experience delivering high-performance ASICs in production or near-production environments
Strong fundamentals in digital logic, circuits, and process technology
Hands-on experience with timing closure, static timing analysis, and MMMC methodologies
Familiarity with DFT (scan, ATPG, test coverage tradeoffs)
Deep experience with industry tools such as Innovus, ICC2, PrimeTime, Tempus, Calibre
Strong scripting skills (Python, Tcl, shell) with a track record of building scalable automation
Ability to debug complex physical design issues and drive them to resolution independently
Experience improving or building physical design flows and methodologies, not just running them

Nice to have
Experience with advanced nodes (≤7nm)
Exposure to FPGA prototyping or silicon bring-up
Background in ML accelerators, high-frequency trading systems, networking ASICs, or HPC
Comfort working across hardware/software boundaries (RTL, systems, ML)
Experience applying statistical analysis to timing, power, or design data

What Makes This Role Unique
Work on latency-critical systems where performance is the product
High ownership: engineers are trusted to own entire subsystems and flows
Small, collaborative team with direct impact on system-level outcomes
Opportunity to solve non-standard problems that don't fit into traditional PD playbooks
Competitive compensation aligned with top-tier hardware and trading firms

This role offers flexibility to work from any one of the offices in Austin, TX; Boulder, CO; Chicago, IL; New York, NY (USA)
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