C
Senior ASIC Design Engineer
Accepting applicationsCyberCoders · Santa Clara, CA
Full-Time Mid_senior AIASICEthernetMentorPCIe
Posted
2d ago
Category
Design
Experience
Mid_senior
Country
United States
Job Title: Senior ASIC Design Engineer
Job Location: Santa Clara, CA or Boston, MA
Compensation: $150K - $250K base DOE plus equity
Requirements: ASIC Design, RTL (Verilog/SystemVerilog), Microarchitecture, UCIe / Ethernet / High-Speed I/O, AI Accelerator, Memory Subsystem Design
Position Overview
We are seeking a highly skilled Senior ASIC Design Engineer to lead the design and development of advanced ASIC solutions. The ideal candidate will have a strong background in ASIC design and a passion for innovation in silicon architecture, particularly in AI datacenter applications.
Key Responsibilities
Lead the design and development of complex ASIC projects from concept to production.
Develop RTL code using Verilog and SystemVerilog for various components including Microarchitecture and SOC designs.
Collaborate with cross-functional teams to define requirements and deliver optimized designs that meet product specifications.
Perform extensive verification and validation of designs to ensure high-quality outputs and compliance with standards.
Engage in IP design and integration, focusing on Ethernet, UCIe, UALink, and HBM technologies.
Contribute to the architecture and design of memory subsystems and cache coherence mechanisms.
Mentor junior engineers and provide technical guidance on best practices in ASIC design.
Qualifications
Bachelor's (Master's or PhD preferred) in Electrical Engineering, Computer Engineering, or related field.
5+ years of experience in ASIC design and development.
Proficient in RTL design using Verilog and SystemVerilog.
Strong understanding of Microarchitecture, SOC design, and IP design practices.
Experience with Ethernet, UCIe, PCIe, UALink, and HBM technologies.
Familiarity with silicon architecture concepts, particularly in AI datacenter applications.
Knowledge of memory subsystem design and cache coherence strategies.
Benefits
Competitive salary commensurate with experience including base salary, performance-based bonus, and early-stage equity grant
Comprehensive benefits including health, dental, vision, and life insurance
Well-equipped, sunny offices in Santa Clara, CA and Boston, MA
Relocation assistance and visa sponsorship
Perks include a daily lunch stipend, 401k match, and more
A collaborative, continuous-learning work environment with smart, dedicated colleagues engaged in developing the next generation of architecture for high-performance computing
Email Your Resume In Word To
Mike.Vandenbergh@CyberCoders.com
Looking forward to receiving your resume through our website and going over the position with you. Clicking apply is the best way to apply.
Please do NOT change the email subject line in any way. You must keep the JobID: linkedin : MV1-1980923L340 -- in the email subject line for your application to be considered.
Mike Vandenbergh - Lead Recruiter
For this position, you must be currently authorized to work in the United States without the need for sponsorship for a non-immigrant visa. This is a new role.
CyberCoders will consider for Employment in the City of Los Angeles qualified Applicants with Criminal Histories in a manner consistent with the requirements of the Los Angeles Fair Chance Initiative for Hiring (Ban the Box) Ordinance.
This job was first posted by CyberCoders on 03/18/2026 and applications will be accepted on an ongoing basis until the position is filled or closed.
Everforth CyberCoders is proud to be an Equal Opportunity Employer
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, age, sexual orientation, gender identity or expression, national origin, ancestry, citizenship, genetic information, registered domestic partner status, marital status, status as a crime victim, disability, protected veteran status, or any other characteristic protected by law. Our hiring process includes AI screening for keywords and minimum qualifications, and a virtual recruiter as part of the application process. A human recruiter reviews all results. Click here for details on our virtual recruiter . Everforth CyberCoders will consider qualified applicants with criminal histories in a manner consistent with the requirements of applicable state and local law, including but not limited to the Los Angeles County Fair Chance Ordinance, the San Francisco Fair Chance Ordinance, and the California Fair Chance Act. Everforth CyberCoders is committed to working with and providing reasonable accommodation to individuals with physical and mental disabilities. Individuals needing special assistance or an accommodation while seeking employment can contact a member of our Human Resources team at Benefits@CyberCoders.com to make arrangements.
Copyright © 2026 Everforth, Inc. All rights reserved.
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Job Location: Santa Clara, CA or Boston, MA
Compensation: $150K - $250K base DOE plus equity
Requirements: ASIC Design, RTL (Verilog/SystemVerilog), Microarchitecture, UCIe / Ethernet / High-Speed I/O, AI Accelerator, Memory Subsystem Design
Position Overview
We are seeking a highly skilled Senior ASIC Design Engineer to lead the design and development of advanced ASIC solutions. The ideal candidate will have a strong background in ASIC design and a passion for innovation in silicon architecture, particularly in AI datacenter applications.
Key Responsibilities
Lead the design and development of complex ASIC projects from concept to production.
Develop RTL code using Verilog and SystemVerilog for various components including Microarchitecture and SOC designs.
Collaborate with cross-functional teams to define requirements and deliver optimized designs that meet product specifications.
Perform extensive verification and validation of designs to ensure high-quality outputs and compliance with standards.
Engage in IP design and integration, focusing on Ethernet, UCIe, UALink, and HBM technologies.
Contribute to the architecture and design of memory subsystems and cache coherence mechanisms.
Mentor junior engineers and provide technical guidance on best practices in ASIC design.
Qualifications
Bachelor's (Master's or PhD preferred) in Electrical Engineering, Computer Engineering, or related field.
5+ years of experience in ASIC design and development.
Proficient in RTL design using Verilog and SystemVerilog.
Strong understanding of Microarchitecture, SOC design, and IP design practices.
Experience with Ethernet, UCIe, PCIe, UALink, and HBM technologies.
Familiarity with silicon architecture concepts, particularly in AI datacenter applications.
Knowledge of memory subsystem design and cache coherence strategies.
Benefits
Competitive salary commensurate with experience including base salary, performance-based bonus, and early-stage equity grant
Comprehensive benefits including health, dental, vision, and life insurance
Well-equipped, sunny offices in Santa Clara, CA and Boston, MA
Relocation assistance and visa sponsorship
Perks include a daily lunch stipend, 401k match, and more
A collaborative, continuous-learning work environment with smart, dedicated colleagues engaged in developing the next generation of architecture for high-performance computing
Email Your Resume In Word To
Mike.Vandenbergh@CyberCoders.com
Looking forward to receiving your resume through our website and going over the position with you. Clicking apply is the best way to apply.
Please do NOT change the email subject line in any way. You must keep the JobID: linkedin : MV1-1980923L340 -- in the email subject line for your application to be considered.
Mike Vandenbergh - Lead Recruiter
For this position, you must be currently authorized to work in the United States without the need for sponsorship for a non-immigrant visa. This is a new role.
CyberCoders will consider for Employment in the City of Los Angeles qualified Applicants with Criminal Histories in a manner consistent with the requirements of the Los Angeles Fair Chance Initiative for Hiring (Ban the Box) Ordinance.
This job was first posted by CyberCoders on 03/18/2026 and applications will be accepted on an ongoing basis until the position is filled or closed.
Everforth CyberCoders is proud to be an Equal Opportunity Employer
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, age, sexual orientation, gender identity or expression, national origin, ancestry, citizenship, genetic information, registered domestic partner status, marital status, status as a crime victim, disability, protected veteran status, or any other characteristic protected by law. Our hiring process includes AI screening for keywords and minimum qualifications, and a virtual recruiter as part of the application process. A human recruiter reviews all results. Click here for details on our virtual recruiter . Everforth CyberCoders will consider qualified applicants with criminal histories in a manner consistent with the requirements of applicable state and local law, including but not limited to the Los Angeles County Fair Chance Ordinance, the San Francisco Fair Chance Ordinance, and the California Fair Chance Act. Everforth CyberCoders is committed to working with and providing reasonable accommodation to individuals with physical and mental disabilities. Individuals needing special assistance or an accommodation while seeking employment can contact a member of our Human Resources team at Benefits@CyberCoders.com to make arrangements.
Copyright © 2026 Everforth, Inc. All rights reserved.
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