Senior Architect – Physical Design

Senior Architect – Physical Design
Location: Bengaluru
Experience: 15–20 Years
Role Overview
Seeking a Senior Architect – Physical Design to lead implementation architecture and signoff of complex SoCs across advanced technology nodes. The role requires deep expertise in PPA optimization, hierarchical design methodologies, and full-chip physical implementation.
Key Responsibilities
Define and drive physical design architecture for large-scale SoCs and high-performance IPs.
Own end-to-end implementation from floorplanning through signoff.
Lead partitioning, power planning, clock architecture, CTS, routing, and ECO closure.
Drive timing, power, congestion, IR/EM, and physical verification closure.
Architect methodologies for PPA optimization across advanced nodes.
Collaborate with RTL, STA, DFT, Packaging, and Foundry teams to ensure design convergence.
Drive automation and flow enhancement using Tcl, Python, and Perl.
Mentor technical teams and provide architectural guidance for complex programs.
Technical Skills
Strong expertise in Floorplanning, Power Planning, CTS, Place & Route, ECO, and Signoff.
Hands-on experience with Synopsys ICC2/Fusion Compiler and Cadence Innovus.
Deep understanding of STA, SI, IR Drop, EM, Crosstalk, and Physical Verification.
Expertise in advanced-node designs (7nm/5nm/3nm and below) and hierarchical SoC implementation.
Experience with PrimeTime, StarRC, RedHawk/Voltus, and Calibre signoff flows.
Strong scripting skills in Tcl, Python, and Perl.
Exposure to chip-package co-design, low-power implementation, and multi-voltage architectures is desirable.
Qualifications
B.E./B.Tech/M.E./M.Tech in Electronics, VLSI, or related disciplines.
Proven track record of delivering multiple high-performance SoCs to silicon with architectural ownership.
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