Senior Analog Layout engineers

Role and Responsibilities
• Responsible for layout design and development of critical analog, mixed-signal, custom digital block, standard cells and full chip level.
• Perform layout verification like LVS, DRC, Antenna, Shield, Matching, Latch up, EM IR Totem checks, quality check and documentation.
• Responsible for development of digital block layouts using auto placement and route tools
• Responsible for basic understanding of skill coding and automation
• Responsible for on-time delivery of block-level layouts with acceptable quality.
• Demonstrate skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment.
• Effectively communicating with manager to assure the success of layout project.

Qualification/Requirements
• 3 to 5-years' experience in analog/custom layout design in advanced CMOS process.
• Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must.
• Should have hands on experience in creating layout of critical blocks such as Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc.,
• Good understanding of Analog Layout fundamentals (e.g., Matching, Electro-migration, Latch-up, coupling, crosstalk, IR-drop, active and passive parasitic devices etc.)
• Understanding layout effects on the circuit such as speed, capacitance, power and area etc.,
• Ability to understand design constraints and implement high-quality layouts.
• Excellent command and problem-solving skills in physical verification of custom layout.
Excellent verbal and written communication skills.

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