Senior Analog Layout Engineer

Company Description CoreIC Technologies is a specialized engineering partner focused on Semiconductor, Embedded Systems, and Digital Engineering solutions. The company supports clients in accelerating innovation, scaling engineering teams, and improving product delivery speed and quality. With expertise spanning advanced chip design, cloud-native platforms, data and AI engineering, and cloud & DevOps, CoreIC Technologies brings deep domain knowledge to complex technical programs. Teams rely on CoreIC to remove delivery bottlenecks, accelerate releases, and keep critical initiatives on track without waiting for lengthy hiring cycles. CoreIC also emphasizes quality and security through robust QA, performance testing, and cloud security practices.
Role Description The Senior Analog Layout Engineer is a full-time, on-site role based in Bengaluru South. This position is responsible for translating analog and mixed-signal circuit schematics into high-quality, manufacturable layouts that meet performance, reliability, and area targets. Day-to-day activities include floorplanning, transistor-level placement, routing of sensitive analog nodes, device matching, and adherence to foundry design rules and ESD/EM requirements. The engineer collaborates closely with circuit design teams to review layout intent, perform layout-versus-schematic (LVS) and design rule checks (DRC), and iterate to optimize noise, parasitics, and yield. The role also involves participating in design reviews, documenting layout constraints and guidelines, mentoring junior layout engineers, and supporting tape-out and post-silicon debug as needed.
Qualifications
Strong expertise in analog and mixed-signal layout for IPs such as amplifiers, ADC/DACs, PLLs, bandgaps, comparators, and sensor interfaces.
Hands-on experience with industry-standard layout tools (e.g., Cadence Virtuoso, Mentor/Siemens, Synopsys) and PDKs for leading foundries.
Proficiency in DRC, LVS, ERC, and reliability checks, including ESD, electromigration, and latch-up prevention techniques.
Solid understanding of device physics, matching, common-centroid layout, shielding, guard rings, and parasitic impact on analog performance.
Ability to interpret circuit schematics, constraints, and specifications, and translate them into robust floorplans and layout architectures.
Experience working across process nodes (e.g., CMOS, BiCMOS, advanced nodes and legacy nodes) and familiarity with tape-out flows.
Strong collaboration skills to work with analog design, digital design, verification, and physical design teams in a cross-functional environment.
Attention to detail, ownership mindset, and ability to manage multiple blocks and schedules while maintaining quality.
Bachelor’s or Master’s degree in Electronics, Electrical
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