SP
Senior Analog Layout Design Engineer
Accepting applicationsSiMaxTech Pvt Ltd · Bengaluru, Karnataka, India
Full-Time Entry Analog LayoutCadence VirtuosoCalibreDRCLVS
Estimated market salary
₹19-33 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
3d ago
Category
Design
Experience
Entry
Country
India
Company Description SiMaxTech Pvt Ltd is a fast-growing semiconductor design services company that delivers end-to-end chip solutions to global customers. The organization has strong capabilities across the semiconductor design spectrum, including Analog Circuit Design, RTL Design, Design Verification, Custom Layout, Physical Design, AMS Verification, Embedded Design, and full-chip SoC backend design. With expertise spanning process technologies from mature nodes like 65nm, 40nm, and 28nm to advanced nodes such as 7nm, 5nm, 3nm, and emerging nodes like 2nm and 18A, SiMaxTech supports next-generation, high-performance, and reliable semiconductor products. The company focuses on continuous learning, innovation, and execution excellence to provide holistic support across the entire chip development lifecycle. Its vision is to be the preferred semiconductor design services partner worldwide, backed by a skilled engineering team and a customer-centric approach.
Role Description The Lead Analog Layout Design Engineer will be responsible for driving custom analog layout design for complex circuits and IP blocks, ensuring robust implementation that meets performance, area, and reliability requirements. This full-time, on-site role is based in Hosur and involves close collaboration with circuit design engineers to translate schematics into optimized layouts, perform layout-versus-schematic (LVS) and design rule checks (DRC), and resolve physical verification issues. Day-to-day activities include floor planning, device matching, parasitic-aware layout optimization, and adherence to foundry-specific design guidelines across multiple technology nodes. The role also includes mentoring junior layout engineers, reviewing their work for quality and consistency, contributing to layout methodologies and best practices, and coordinating with cross-functional teams to support tape-out and post-silicon debug.
Experience: 5+ years
Location: Bengaluru
Notice Period: Immediate to 30 Days
Qualifications
Strong proficiency in analog Layout Design and Custom Layout for complex blocks and SoCs.
Hands-on experience in Analog Circuit Design and Analog Circuits, including matched devices, current mirrors, amplifiers, and data converters.
Solid understanding of Circuit Design fundamentals and analog design principles such as noise, mismatch, and layout-dependent effects.
Practical experience with Physical Verification flows, including DRC, LVS, ERC, and electrostatic discharge (ESD) checks.
Proficiency with industry-standard EDA tools for layout and verification (e.g., Cadence Virtuoso, Mentor/Siemens Calibre, Synopsys tools).
Experience working across multiple technology nodes, preferably including advanced nodes (e.g., 28nm and below).
Ability to lead, mentor, and review the work of layout engineers, with strong ownership and attention to detail.
Effective communication and collaboration skills to work with cross-functional design, verification,
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Role Description The Lead Analog Layout Design Engineer will be responsible for driving custom analog layout design for complex circuits and IP blocks, ensuring robust implementation that meets performance, area, and reliability requirements. This full-time, on-site role is based in Hosur and involves close collaboration with circuit design engineers to translate schematics into optimized layouts, perform layout-versus-schematic (LVS) and design rule checks (DRC), and resolve physical verification issues. Day-to-day activities include floor planning, device matching, parasitic-aware layout optimization, and adherence to foundry-specific design guidelines across multiple technology nodes. The role also includes mentoring junior layout engineers, reviewing their work for quality and consistency, contributing to layout methodologies and best practices, and coordinating with cross-functional teams to support tape-out and post-silicon debug.
Experience: 5+ years
Location: Bengaluru
Notice Period: Immediate to 30 Days
Qualifications
Strong proficiency in analog Layout Design and Custom Layout for complex blocks and SoCs.
Hands-on experience in Analog Circuit Design and Analog Circuits, including matched devices, current mirrors, amplifiers, and data converters.
Solid understanding of Circuit Design fundamentals and analog design principles such as noise, mismatch, and layout-dependent effects.
Practical experience with Physical Verification flows, including DRC, LVS, ERC, and electrostatic discharge (ESD) checks.
Proficiency with industry-standard EDA tools for layout and verification (e.g., Cadence Virtuoso, Mentor/Siemens Calibre, Synopsys tools).
Experience working across multiple technology nodes, preferably including advanced nodes (e.g., 28nm and below).
Ability to lead, mentor, and review the work of layout engineers, with strong ownership and attention to detail.
Effective communication and collaboration skills to work with cross-functional design, verification,
Show more Show less