WA

Senior Analog Circuit Design Engineer

Accepting applications

Weekday AI (YC W21) · Bengaluru, Karnataka, India

Full-Time Mid_senior PMICDC-DC ConverterAnalog Circuit DesignSimulationCadence
Estimated market salary
₹59-106 LPA

This is a SiliconBoard market estimate, not an employer-posted salary.

Posted
2d ago
Category
Design
Experience
Mid_senior
Country
India
This role is for one of the Weekday's clients

Salary range: Rs 2500000 - Rs 4000000 (ie INR 25-40 LPA)

Min Experience: 6+ years

Location: Bengaluru

JobType: full-time

We are looking for a Senior Analog Circuit Design Engineer with strong expertise in Power Management IC (PMIC) design to develop high-performance DC-DC switching converters. The ideal candidate should have hands-on experience designing both high-voltage (up to 40V) and low-voltage (around 5V) switching converters, with a deep understanding of peak current mode control architectures.

In this role, you will own complete analog IPs or buck converter top-level designs, perform transistor-level and post-layout simulations, mentor junior engineers, and collaborate with cross-functional teams to deliver robust power management solutions.

Requirements

Key Responsibilities

Analog Circuit Design

Design and develop analog circuits for Power Management IC (PMIC) applications.
Own the design and development of DC-DC buck converter IPs from specification through verification.
Design and optimize both high-voltage and low-voltage switching converter architectures.
Develop and validate peak current mode control circuitry for efficient power conversion.

Simulation & Verification

Perform transistor-level and top-level circuit simulations to validate design functionality and performance.
Execute post-layout extraction (PEX) simulations for sub-blocks and complete analog IPs.
Analyze simulation results and optimize designs for power, efficiency, stability, and performance.
Support silicon validation by investigating and resolving analog design issues.

Design Ownership

Take ownership of complete analog IPs or buck converter top-level designs throughout the development lifecycle.
Implement sub-block enhancements, design modifications, and bug fixes.
Ensure designs meet performance, reliability, and manufacturability requirements.

Technical Leadership

Mentor and guide junior engineers through design reviews and technical discussions.
Review schematics, simulation results, and design implementations to maintain high engineering standards.
Collaborate with layout, verification, and system teams to ensure successful project execution.
Contribute to design methodology improvements and best practices.

Required Qualifications

Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, or a related field.
Strong experience in Analog IC Design with emphasis on Power Management ICs (PMICs).
Hands-on experience designing DC-DC switching converters, including high-voltage and low-voltage buck converters.
Strong understanding of Peak Current Mode Control architectures.
Experience owning analog IP development from design through verification.
Proficiency in transistor-level simulation and circuit optimization.
Experience performing PEX simulations at both sub-block and top-level.
Strong debugging, analytical, and problem-solving skills.
Excellent communication and leadership abilities.

Preferred Qualifications

Experience with high-voltage switching converters (up to 40V).
Experience with low-voltage switching converters (around 5V).
Familiarity with analog layout considerations and post-layout verification.
Experience mentoring engineers and leading technical reviews.
Knowledge of mixed-signal integration and PMIC architectures.

Must-Have Skills

Analog IC Design
Power Management IC (PMIC)
DC-DC Converter Design
Buck Converter Design
Peak Current Mode Control
Analog Circuit Simulation
PEX Simulation
Analog IP Design

Good-to-Have Skills

Analog Circuit Design
High-Voltage Converter Design
Low-Voltage Converter Design
Post-Layout Verification
Mixed-Signal Design
Power Electronics
Technical Leadership
Analog Layout Collaboration
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