IG
Senior AMS Verification Engineer
Accepting applicationsInsight Global · Chandler, AZ
Full-Time Mid_senior SystemVerilogUVMVeriloganalogmixed-signal
Posted
4d ago
Category
Verification
Experience
Mid_senior
Country
United States
This role will lead analog and mixed-signal verification for automotive and industrial PMIC products from specification through verification signoff. It will also define verification strategies, environments, regressions, and coverage objectives for complex mixed-signal IPs, subsystems, and SoCs. Collaborate with cross-functional teams to ensure product quality, reliability, functional correctness, safety, and robustness.
Review product requirements, architecture specifications, design documentation, programming models, interfaces, and implementation plans for automotive and industrial PMIC applications.
Define and execute AMS verification strategies aligned with system, performance, quality, reliability, safety, power, and functional requirements.
Lead AMS verification activities, including verification plans, methodologies, environments, regressions, documentation, schedules, coverage objectives, and milestone tracking.
Develop and validate mixed-signal simulation environments, behavioral models, checkers, assertions, scoreboards, and reusable verification components using Verilog-AMS, SystemVerilog, UVM, and RNM.
Drive verification execution through test planning, constrained-random verification, mixed-signal simulation, coverage analysis, regression management, debug, and signoff.
Bridge digital and mixed-signal verification flows for robust block, subsystem, and top-level verification
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Review product requirements, architecture specifications, design documentation, programming models, interfaces, and implementation plans for automotive and industrial PMIC applications.
Define and execute AMS verification strategies aligned with system, performance, quality, reliability, safety, power, and functional requirements.
Lead AMS verification activities, including verification plans, methodologies, environments, regressions, documentation, schedules, coverage objectives, and milestone tracking.
Develop and validate mixed-signal simulation environments, behavioral models, checkers, assertions, scoreboards, and reusable verification components using Verilog-AMS, SystemVerilog, UVM, and RNM.
Drive verification execution through test planning, constrained-random verification, mixed-signal simulation, coverage analysis, regression management, debug, and signoff.
Bridge digital and mixed-signal verification flows for robust block, subsystem, and top-level verification
Show more Show less