Security Operations Center Architect

RTL Design / Digital (Logic) Design Engineer
Locations: Bay Area, Austin, Dallas

The role is related to High Bandwidth Memory (HBM). The program involves building a custom chip around the HBM piece by working with memory vendors. This highly strategic program requires leveraging external vendors extensively, and initially, they plan to work with one of the three big HBM vendors—Samsung, Hynix, and Micron—but will eventually need to work with all of them in parallel due to high demand

Details of expertise:
Project experience with ARM based ecosystem components
M7, Coresight, NIC, and other AMBA bus interconnect
Familiarity with AMBA bus protocols and SoC system debug infrastructure
Strong experience with micro-architecture, Verilog/ System Verilog, Synthesis, timing constraints development, Lint, CDC checks
Understanding of SoC interfaces like QSPI, UART, and GPIOs
Capable of working with multiple IP vendors and other IP teams
Strong experience with UVM based verification, setting up co-simulation environments with ARM CPU models
Plus points: experience with DRAM memory controllers and its interfaces
Plus points: experience with UCIe
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