IP
SDC Engineer
Accepting applicationsiTek People Inc · San Jose, CA
Contract Entry ASICDFTPerlPythonRTL
Posted
22h ago
Category
Design
Experience
Entry
Country
United States
Job Title: Senior ASIC Design / SDC & STA Engineer
Target Experience: 10+ Years (Senior / Lead Subcon)
Domain: Networking Silicon / High-Performance ASIC
Certifications Needed: No
Location / Modality: Hybrid / Onsite (Face-to-Face Required for Final Round)
Role Overview
We are seeking an experienced Senior ASIC Design / SDC Engineer with deep expertise in static timing analysis (STA) and timing constraints development. In this role, you will own block-level and full-chip SDC generation, validation, and signoff across multiple operational and test modes for next-generation high-performance networking chips. You will collaborate directly with Architecture, Front-End RTL, DFT, and Physical Design teams to resolve complex clocking architectures, asynchronous domain crossings, and ensure seamless timing closure.
Top 3 Core Responsibilities
End-to-End Timing Constraints (SDC) Ownership: Author, refine, and promote timing constraints from block level to full chip (and budget/push down from top to block) across all functional, test, and low-power modes.
Constraint Verification & Quality Signoff: Validate SDC correctness using industry-standard tools (e.g., TCM, TimeVision, Fishtail) to catch missing constraints, conflicting clock groups, invalid false/multicycle paths, and duty-cycle/jitter inaccuracies prior to Physical Design handoff.
Cross-Functional Architecture & Timing Closure Support: Work closely with RTL and Physical Design/STA teams to define clocking specifications, debug asynchronous clock domain crossings (CDC), analyze timing reports, and recommend architectural or constraint fixes for physical timing closure.
Key Responsibilities & Deliverables
Develop and maintain robust SDC files for multi-million-gate blocks and full-chip hierarchy.
Analyze complex clocking schemes, including PLL outputs, multiplexed clocks, clock gating, and generated divider clocks.
Review clocking architecture diagrams and maintain timing constraint documentation.
Write custom TCL and Shell scripts to automate constraint generation, linting, and STA run flows.
Support synthesis and implementation iterations with Synopsys DC/DCG/FC and Primetime.
Optional participation in block-level RTL microarchitecture, coding, or IP integration based on project phase.
Qualifications & Skills
Must-Have (Required):
Experience: 10+ years of hands-on ASIC design, timing constraints development, and STA closure.
Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, VLSI, or a related technical discipline.
SDC & STA Tool Expertise: Proven track record using Synopsys PrimeTime (or equivalent) and constraint verification tools such as TCM or TimeVision.
Synthesis & Implementation Flow: Practical experience with Synopsys Design Compiler (DC / DC-NXT) or Fusion Compiler (FC).
Clocking & Digital Design: Solid command of clock domain crossing (CDC), asynchronous boundaries, multi-frequency domains, false paths, and multicycle paths.
Scripting: Advanced scripting skills in TCL; working knowledge of Perl, Python, or Shell scripting for flow automation.
HDL: Proficiency in Verilog or SystemVerilog for RTL tracing and debug.
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Target Experience: 10+ Years (Senior / Lead Subcon)
Domain: Networking Silicon / High-Performance ASIC
Certifications Needed: No
Location / Modality: Hybrid / Onsite (Face-to-Face Required for Final Round)
Role Overview
We are seeking an experienced Senior ASIC Design / SDC Engineer with deep expertise in static timing analysis (STA) and timing constraints development. In this role, you will own block-level and full-chip SDC generation, validation, and signoff across multiple operational and test modes for next-generation high-performance networking chips. You will collaborate directly with Architecture, Front-End RTL, DFT, and Physical Design teams to resolve complex clocking architectures, asynchronous domain crossings, and ensure seamless timing closure.
Top 3 Core Responsibilities
End-to-End Timing Constraints (SDC) Ownership: Author, refine, and promote timing constraints from block level to full chip (and budget/push down from top to block) across all functional, test, and low-power modes.
Constraint Verification & Quality Signoff: Validate SDC correctness using industry-standard tools (e.g., TCM, TimeVision, Fishtail) to catch missing constraints, conflicting clock groups, invalid false/multicycle paths, and duty-cycle/jitter inaccuracies prior to Physical Design handoff.
Cross-Functional Architecture & Timing Closure Support: Work closely with RTL and Physical Design/STA teams to define clocking specifications, debug asynchronous clock domain crossings (CDC), analyze timing reports, and recommend architectural or constraint fixes for physical timing closure.
Key Responsibilities & Deliverables
Develop and maintain robust SDC files for multi-million-gate blocks and full-chip hierarchy.
Analyze complex clocking schemes, including PLL outputs, multiplexed clocks, clock gating, and generated divider clocks.
Review clocking architecture diagrams and maintain timing constraint documentation.
Write custom TCL and Shell scripts to automate constraint generation, linting, and STA run flows.
Support synthesis and implementation iterations with Synopsys DC/DCG/FC and Primetime.
Optional participation in block-level RTL microarchitecture, coding, or IP integration based on project phase.
Qualifications & Skills
Must-Have (Required):
Experience: 10+ years of hands-on ASIC design, timing constraints development, and STA closure.
Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, VLSI, or a related technical discipline.
SDC & STA Tool Expertise: Proven track record using Synopsys PrimeTime (or equivalent) and constraint verification tools such as TCM or TimeVision.
Synthesis & Implementation Flow: Practical experience with Synopsys Design Compiler (DC / DC-NXT) or Fusion Compiler (FC).
Clocking & Digital Design: Solid command of clock domain crossing (CDC), asynchronous boundaries, multi-frequency domains, false paths, and multicycle paths.
Scripting: Advanced scripting skills in TCL; working knowledge of Perl, Python, or Shell scripting for flow automation.
HDL: Proficiency in Verilog or SystemVerilog for RTL tracing and debug.
Show more Show less