S
S Design Verification Engineer
Accepting applicationsSivaltech · San Francisco Bay Area
Full-Time Entry ASICC++RTLSoCSystemVerilog
Posted
2d ago
Category
Verification
Experience
Entry
Country
United States
🚀 Hiring: Design Verification Engineer (Chip-Level Verification)
Sivaltech is seeking experienced Design Verification Engineers with strong Chip-Level Verification expertise to join our growing team.
📍 Location: Bay Area, CA / Remote (as applicable)
📅 Experience: 6+ Years
Key Responsibilities:
• Develop and execute comprehensive chip-level verification plans for complex SoCs
• Build and maintain SystemVerilog/UVM-based verification environments
• Create test cases, checkers, scoreboards, and coverage models
• Drive functional, code, assertion, and toggle coverage closure
• Debug RTL and verification environment issues
• Collaborate closely with Design, Architecture, Firmware, and Post-Silicon teams
• Perform regression analysis and root-cause failure investigations
• Validate subsystem integration and end-to-end chip functionality
Required Skills:
• Strong expertise in SystemVerilog and UVM
• Extensive experience in Chip-Level Verification
• Experience with SoC verification methodologies and verification planning
• Strong debugging skills in simulation and regression environments
• Experience with Assertions (SVA) and Coverage-Driven Verification
• Knowledge of industry-standard simulators (VCS, Xcelium, Questa)
• Experience with AMBA protocols (AXI, AHB, APB)
• Familiarity with low-power verification concepts is a plus
• Experience with C/C++ or embedded software validation is desirable
Qualifications:
• Bachelor's or Master's Degree in Electronics/Electrical Engineering
• 6+ years of Design Verification experience with significant chip-level verification exposure
• Proven experience in successful SoC/ASIC tape-outs
📩 Interested candidates can share their updated resume or connect with us directly.
#Hiring #DesignVerification #DVEngineer #SystemVerilog #UVM #ChipLevelVerification #SoCVerification #ASIC #Semiconductor #VLSI #Sivaltech
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Sivaltech is seeking experienced Design Verification Engineers with strong Chip-Level Verification expertise to join our growing team.
📍 Location: Bay Area, CA / Remote (as applicable)
📅 Experience: 6+ Years
Key Responsibilities:
• Develop and execute comprehensive chip-level verification plans for complex SoCs
• Build and maintain SystemVerilog/UVM-based verification environments
• Create test cases, checkers, scoreboards, and coverage models
• Drive functional, code, assertion, and toggle coverage closure
• Debug RTL and verification environment issues
• Collaborate closely with Design, Architecture, Firmware, and Post-Silicon teams
• Perform regression analysis and root-cause failure investigations
• Validate subsystem integration and end-to-end chip functionality
Required Skills:
• Strong expertise in SystemVerilog and UVM
• Extensive experience in Chip-Level Verification
• Experience with SoC verification methodologies and verification planning
• Strong debugging skills in simulation and regression environments
• Experience with Assertions (SVA) and Coverage-Driven Verification
• Knowledge of industry-standard simulators (VCS, Xcelium, Questa)
• Experience with AMBA protocols (AXI, AHB, APB)
• Familiarity with low-power verification concepts is a plus
• Experience with C/C++ or embedded software validation is desirable
Qualifications:
• Bachelor's or Master's Degree in Electronics/Electrical Engineering
• 6+ years of Design Verification experience with significant chip-level verification exposure
• Proven experience in successful SoC/ASIC tape-outs
📩 Interested candidates can share their updated resume or connect with us directly.
#Hiring #DesignVerification #DVEngineer #SystemVerilog #UVM #ChipLevelVerification #SoCVerification #ASIC #Semiconductor #VLSI #Sivaltech
Show more Show less