MT
RTL/SDC Engineer
Accepting applicationsMirafra Technologies · San Jose, CA
Full-Time Mid_senior CadenceDFTRTLSynopsysmentor
Posted
2d ago
Category
Design
Experience
Mid_senior
Country
United States
Being a member of design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes.
Helping develop efficient methodology to promote block level SDCs to fullchip, and to bring fullchip SDC changes back to block level.
Helping develop and apply methodology to ensure correctness and quality of SDCs as early as possible in design cycle.
Reviewing block level SDCs and clocking diagrams and mentor other RTL design owners on SDC development.
Leading the fullchip clocking design including diagrams and related documentation.
Preferred Qualifications:
Experience in Static Timing Analysis.
Experience with constraint analyzer tools such as Fishtail/TCM (Timing Constraint Manager from Synopsys) and CCD (Conformal Constraint Designer from Cadence).
Experience with Spyglass CDC and glitch analysis.
Show more Show less
Helping develop efficient methodology to promote block level SDCs to fullchip, and to bring fullchip SDC changes back to block level.
Helping develop and apply methodology to ensure correctness and quality of SDCs as early as possible in design cycle.
Reviewing block level SDCs and clocking diagrams and mentor other RTL design owners on SDC development.
Leading the fullchip clocking design including diagrams and related documentation.
Preferred Qualifications:
Experience in Static Timing Analysis.
Experience with constraint analyzer tools such as Fishtail/TCM (Timing Constraint Manager from Synopsys) and CCD (Conformal Constraint Designer from Cadence).
Experience with Spyglass CDC and glitch analysis.
Show more Show less