RTL Integration Engineer

About the company:
Our client is a rapidly growing semiconductor engineering and technology services organization delivering end-to-end solutions to global technology companies. With expertise spanning ASIC design, verification, physical design, DFT, circuit design and layout, FPGA design, and emulation, the organization supports customers across the semiconductor development lifecycle. Known for its focus on engineering excellence, innovation, high-quality delivery, and shorter development cycles, the company provides professionals with opportunities to work on challenging, next-generation semiconductor technologies in a collaborative and growth-oriented environment.

Job Summary:
We are seeking an experienced RTL Integration Engineer to join our front-end engineering team and drive the integration of third-party IPs into complex digital subsystems. The ideal candidate will be responsible for RTL integration, subsystem development, CDC analysis, bus interface implementation, and collaboration between digital and analog/mixed-signal teams. This role requires strong expertise in SystemVerilog, IP integration, linting, CDC verification, and functional safety requirements within advanced semiconductor designs.

Key Responsibilities:
Lead the integration of third-party IPs into complex digital subsystems.
Own the complete RTL integration process, including architecture, implementation, validation, and maintenance.
Integrate and validate PHY components within the digital subsystem.
Design and implement asynchronous FIFO architectures and data-path solutions.
Develop and maintain bus bridges, register maps, and control/status register (CSR) implementations.
Perform multi-clock and multi-domain Clock Domain Crossing (CDC) analysis.
Conduct RTL quality checks, linting, and lint closure activities using industry-standard tools.
Collaborate with analog and mixed-signal teams to perform co-simulations and resolve integration challenges.
Support MBIST, LBIST, redundancy, and other design-for-test implementations.
Contribute to implementing safety mechanisms to ensure compliance with Functional Safety (FuSa) requirements.
Review design specifications, PHY documentation, and interface requirements to ensure successful integration.
Work closely with architecture, verification, physical design, and DFT teams throughout the development lifecycle.
Participate in debugging, issue resolution, design reviews, and technical discussions.

Required Technical Skills:
Strong experience in RTL design and third-party IP integration.
Hands-on experience with SystemVerilog, including RTL development and assertions.
Experience with multi-domain CDC analysis.
Knowledge of asynchronous FIFO design and data-path implementation.
Experience with APB and SoC bus architectures.
Familiarity with RGGEN-based CSR methodologies.
Hands-on experience with Cadence HAL, SpyGlass, and CDC verification tools.
Understanding of PHY integration and related protocols.
Experience with digital and analog/mixed-signal co-simulations.
Knowledge of MBIST, LBIST, redundancy implementation, and DFT concepts.
Familiarity with Functional Safety (FuSa) requirements and safety mechanisms.

Preferred Qualifications:
Working knowledge of ASA-ML DLL, PCS, OAM, PTB, and ASEP layers.
Ability to interpret and work with PHY datasheets and technical specifications.
Strong debugging, problem-solving, and analytical skills.
Excellent communication and cross-functional collaboration skills.

Qualifications & Experience:
B.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, VLSI, or a related field.
8–12 years of relevant industry experience in RTL design and IP integration.

Travel Requirements:
Travel may be required based on project and client requirements.

Show more Show less