RTL Engineer, Networking ASIC

RTL Engineer, Networking ASIC

San Jose, CA

Our client is a Silicon Valley-based hardware startup pioneering infrastructure solutions that accelerate AI data centers to deliver Faster AI. Today’s AI performance is frequently limited by communication bottlenecks

.
Our client introduces multiple industry-first innovations across silicon, packaging, software, and systems to deliver sharp improvement in performance and greater GPU utilization to speed training job completion times and tokens-per-second for more profitable inferenc

e.The company’s solutions and value proposition are validated by leading hyperscaler

s.
Our client has raised over $200M including a recent Series A round. The company is led by a team of Silicon Valley executives who have delivered multiple product lines and led multiple companies to billion dollar exi

ts.
The company has a world-class engineering team with decades of experience in state-of-the-art silicon, packaging, optics, software, and syst

ems.
Position Ove

rviewWe are seeking experienced RTL designers to help define and implement our industry-leading Networking ASIC’s. If you're a highly motivated self-starter eager to solve real-world problems, this is a unique opportunity to shape the future of AI Networking. As part of the Design Group, you will be responsible for defining, specifying, architecting, executing, and productizing cutting-edge Networking c

hips.
Responsibil

• ities Packet buffering, queuing, and scheduling: Work on micro architecture and design implementation of high-speed networking ASIC’s, focusing on latency optimization and quality of service (QoS) support. Prior experience with on-chip memory subsystem and scheduling / arbitration d
• esign.Implementation and Testing: Implement designs on ASIC platforms, ensuring compliance with industry standards and performance benchmarks. Work with verification team to conduct thorough testing and validation to ensure functionality and reliab
• ility.Performance Optimization: Analyze and optimize pipelining architectures to improve performance me
• trics.Protocol Support: Provide support for various networking protocols such as Ethernet and IP protocols, and high speed interconnects such as
• UCIe.Troubleshooting and Debugging: Investigate and resolve complex issues related to packet queuing, working closely with cross-functional teams, including system architects, hardware engineers, and firmware devel

opers.
Qualifi

cationsME/BE with a minimum of 8-15 years of expe

rience.Hands-on knowledge of System Verilog and Verilog is man

datory.Solid understanding of ASIC design methodologies, including simulation, verification, synthesis, and timing adjus

tments.Proven expertise in designing and optimizing scheduling and QoS mech

anisms.Experience with Ethernet and IP pro

tocols.Strong analytical and problem-solving abilities, with meticulous attention to detail in troubleshooting and debugging complex networking

issues.Excellent verbal and written communication skills, with the ability to collaborate effectively in a team environment and present technical information to diverse aud