S
RTL Engineer
Accepting applicationsSivaltech · San Jose, CA
Full-Time Entry ASICEthernetMentorRTLSoC
Posted
2d ago
Category
Design
Experience
Entry
Country
United States
The ideal candidate will be responsible for implementing electrical components into devices. They will also help design and manufacture electrical products of all shapes and sizes. They should be able to make quality assurance checks in order to keep the product standard high.
Responsibilities
Job Title: Senior RTL Design Engineer – Ethernet
Location: Bay Area, CA (Onsite)
Experience: 9+ Years
Job Description
We are looking for an experienced Senior RTL Design Engineer with strong expertise in Ethernet IP design to join our ASIC/SoC design team. The ideal candidate should have extensive hands-on experience in RTL design, microarchitecture, and high-speed Ethernet protocols for networking or datacenter SoCs.
Required Qualifications
- 9+ years of experience in ASIC/SoC RTL Design.
- Strong expertise in Verilog/SystemVerilog RTL development.
- Hands-on experience designing Ethernet MAC/PCS or other Ethernet IPs.
- Strong knowledge of Ethernet standards (1G/10G/25G/40G/50G/100G/200G/400G Ethernet).
- Experience with high-speed interfaces and bus protocols such as AXI, AHB, or APB.
- Ability to develop microarchitecture from functional specifications and implement high-quality RTL.
- Experience with synthesis, lint, CDC, STA constraints, and design quality checks.
- Strong debugging and problem-solving skills throughout the ASIC development cycle.
- Experience with version control tools such as Git or Perforce.
Responsibilities
- Design and implement RTL for high-performance Ethernet and networking IPs.
- Define and review microarchitecture for complex hardware blocks.
- Work closely with architecture, verification, physical design, and firmware teams.
- Drive RTL quality through design reviews, debugging, and issue resolution.
- Support synthesis, timing closure, and silicon bring-up activities.
- Mentor junior engineers and contribute to design methodology improvements.
Education
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
Location: Bay Area, CA (Onsite)
Experience: 9+ Years
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Responsibilities
Job Title: Senior RTL Design Engineer – Ethernet
Location: Bay Area, CA (Onsite)
Experience: 9+ Years
Job Description
We are looking for an experienced Senior RTL Design Engineer with strong expertise in Ethernet IP design to join our ASIC/SoC design team. The ideal candidate should have extensive hands-on experience in RTL design, microarchitecture, and high-speed Ethernet protocols for networking or datacenter SoCs.
Required Qualifications
- 9+ years of experience in ASIC/SoC RTL Design.
- Strong expertise in Verilog/SystemVerilog RTL development.
- Hands-on experience designing Ethernet MAC/PCS or other Ethernet IPs.
- Strong knowledge of Ethernet standards (1G/10G/25G/40G/50G/100G/200G/400G Ethernet).
- Experience with high-speed interfaces and bus protocols such as AXI, AHB, or APB.
- Ability to develop microarchitecture from functional specifications and implement high-quality RTL.
- Experience with synthesis, lint, CDC, STA constraints, and design quality checks.
- Strong debugging and problem-solving skills throughout the ASIC development cycle.
- Experience with version control tools such as Git or Perforce.
Responsibilities
- Design and implement RTL for high-performance Ethernet and networking IPs.
- Define and review microarchitecture for complex hardware blocks.
- Work closely with architecture, verification, physical design, and firmware teams.
- Drive RTL quality through design reviews, debugging, and issue resolution.
- Support synthesis, timing closure, and silicon bring-up activities.
- Mentor junior engineers and contribute to design methodology improvements.
Education
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
Location: Bay Area, CA (Onsite)
Experience: 9+ Years
Show more Show less