JV
RTL Design Engineer Wireless SoC
Accepting applicationsJobs via Dice · United States
Full-Time Mid_senior BISTDFTRTLSoCSystemVerilog
Posted
1d ago
Category
Design
Experience
Mid_senior
Country
United States
Dice is the leading career destination for tech experts at every stage of their careers. Our client, Key Infotek LLC, is seeking the following. Apply via Dice today!
RTL Design Engineer Wireless SoC (Remote PST)
Location: Remote (must be aligned with PST time zone / willing to work PST hours)
Rate: DOE
We are seeking an experienced RTL Design Engineer to work on next-generation wireless SoC development. The ideal candidate will design and implement high-performance digital blocks and work closely with architecture, analog/mixed-signal, and verification teams to deliver production-quality silicon.
Required Skills
5+ years of hands-on RTL design experience (SystemVerilog / Verilog)
Strong understanding of micro-architecture and RTL implementation from specs
Experience in DSP hardware implementation (filtering, FFT, etc.)
Knowledge of SoC design flows: CDC, power domains, timing constraints, formal verification
Experience with synthesis, linting, simulation, and STA tools
Understanding of DFT concepts (scan, BIST)
Strong debugging and problem-solving skills
Good communication and ability to work in cross-functional teams
Show more Show less
RTL Design Engineer Wireless SoC (Remote PST)
Location: Remote (must be aligned with PST time zone / willing to work PST hours)
Rate: DOE
We are seeking an experienced RTL Design Engineer to work on next-generation wireless SoC development. The ideal candidate will design and implement high-performance digital blocks and work closely with architecture, analog/mixed-signal, and verification teams to deliver production-quality silicon.
Required Skills
5+ years of hands-on RTL design experience (SystemVerilog / Verilog)
Strong understanding of micro-architecture and RTL implementation from specs
Experience in DSP hardware implementation (filtering, FFT, etc.)
Knowledge of SoC design flows: CDC, power domains, timing constraints, formal verification
Experience with synthesis, linting, simulation, and STA tools
Understanding of DFT concepts (scan, BIST)
Strong debugging and problem-solving skills
Good communication and ability to work in cross-functional teams
Show more Show less
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