RTL Design Engineer

Principal RTL Design Engineer- San Francisco Bay Area, CA
Data Centers, Memory Chips, AI

Role Brief:
My client is looking for a Principal RTL Design Engineer to own the microarchitecture and RTL design of next-generation, high-performance memory controllers powering data centers and AI applications.

Responsibilities:
Own end-to-end microarchitecture & RTL for critical, high-performance SoC blocks
Drive PPA and silicon success through data-driven performance, power, timing, and area optimization
Partner across verification & physical design to solve complex issues and deliver robust, production-ready designs
Influence customer success by providing hands-on technical leadership from pre-sales through post-sales delivery

Skillset:
10+ years of ASIC/FPGA design expertise with deep SystemVerilog/Verilog RTL skills and a strong EE foundation.
Hands-on verification & scripting skills across Questa/Incisive/VCS, UVM, Python, Perl, and TCL.
Silicon-savvy design experience spanning synthesis, timing constraints, CDC/RDC, and PPA-aware implementation.
Bonus expertise in high-speed interfaces & memory including AMBA AXI/CHI, HBM, and LPDDR—with strong communication and independent problem-solving skills.

This is an exciting opportunity to join an industry leading semiconductor company who have some of the most exciting chip/silicon IP products on the market. If you are looking for a company that will provide you with career progression and offer an excellent compensation package, then this is the job for you.

Location:
San Francisco Bay area, CA

For immediate consideration please send your resume to tom.ridd@lumicity.io
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