JV
RTL Design Engineer
Accepting applicationsJobs via Dice · United States
Full-Time Mid_senior BISTDFTRTLSoCSystemVerilog
Posted
1d ago
Category
Design
Experience
Mid_senior
Country
United States
Dice is the leading career destination for tech experts at every stage of their careers. Our client, Caspex Corporation, is seeking the following. Apply via Dice today!
5+ years of hands-on RTL design experience (SystemVerilog / Verilog)
Strong understanding of micro-architecture and RTL implementation from specs
Experience in DSP hardware implementation (filtering, FFT, etc.)
Knowledge of SoC design flows: CDC, power domains, timing constraints, formal verification
Experience with synthesis, linting, simulation, and STA tools
Understanding of DFT concepts (scan, BIST)
Strong debugging and problem-solving skills
Good communication and ability to work in cross-functional teams
Show more Show less
5+ years of hands-on RTL design experience (SystemVerilog / Verilog)
Strong understanding of micro-architecture and RTL implementation from specs
Experience in DSP hardware implementation (filtering, FFT, etc.)
Knowledge of SoC design flows: CDC, power domains, timing constraints, formal verification
Experience with synthesis, linting, simulation, and STA tools
Understanding of DFT concepts (scan, BIST)
Strong debugging and problem-solving skills
Good communication and ability to work in cross-functional teams
Show more Show less
Similar Jobs
AD
Senior Engineer, Digital Design Engineering
Analog Devices · Beaverton, OR
TG
ASIC/RTL Design Engineer
TPI Global Solutions · San Jose, CA
SS
Senior Engineer, GPU RTL Power
Samsung Semiconductor · Austin, Texas Metropolitan Area
C
FPGA Verification Engineer II
CesiumAstro · Denver Metropolitan Area