RTL Design Engineer

SoC Interconnect for the next generation System-on-chip (SoC) for smartphones, tablets and other product categories. This position includes but no limited to:-
§ NoC design lead part of BDC infrastructure (NoC/Interconnect) core team
§ Responsible for specification, design and implementation of interconnect and related IP’s
§ Actively work with SoC team, verification team, physical design team, Soc Floorplan, core teams and various other interconnect teams in various other sites
§ Partner with SoC performance team ensuring Interconnect meeting all performance requirement, and with silicon validation team to co-relate pre-silicon and post silicon design assumptions
Required Skills:
§ 5 to 10 years of solid experience in SoC design
§ Understanding of interconnect protocols like AHB/AXI/ACE/ACE-Lite/NoC concepts
§ Good knowledge of Digital Design and RTL development
§ Hands-on experience with SoC Design, Verilog RTL coding
§ Understanding of multi-core ARMv8 CPU architecture, coherency protocols and virtualization.
§ Working knowledge of Synthesis, DC/DCG synthesis with Synopsys design complier, DFT, verification, formal verification, silicon debug
§ Working knowledge of Lint, CDC, PLDRC, CLP etc
§ Good understanding of the design convergence cycle in terms of architecture, micro-architecture, synthesis, timing closure and verification
§ Manage SoC dependencies, planning and tracking of all front-end design related tasks
§ Driving the project milestones across the design, verification and physical implementations
Should possess effective communication and leadership skills

Qualifications
BE/BTech/ME/MTech/MS
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