B
RTL Design Engineer
Accepting applicationsBCforward · United States
Contract Mid_senior RTLSystemVerilogVerilog
Posted
20h ago
Category
Design
Experience
Mid_senior
Country
United States
BCforward is seeking a highly motivated and experienced RTL (Digital) Design Engineer to join our dynamic team.
Position: RTL (Digital) Design Engineer
Work Type: REMOTE
Duration: 12 months (Possible Extension).
Description
We are seeking experienced RTL Design Engineers who can operate independently, collaborate closely with client leads, and commit to full project lifecycle ownership.
1. RTL Design Engineer
Key Responsibilities
Own micro-architecture definition from high-level functional specifications
Develop and implement RTL for complex digital blocks
Drive digital block control and IP integration
Participate in subsystem-level architecture alignment
Support design sign-off activities (CDC, RDC, lint, synthesis readiness)
Collaborate closely with DV for closure and debug
Required Qualifications
Strong expertise in RTL design (SystemVerilog/Verilog)
Experience defining micro-architecture independently
Solid understanding of memory controllers and digital subsystems
Experience with IP integration and block-level ownership
Familiarity with sign-off flows including:
CDC (Clock Domain Crossing)
RDC (Reset Domain Crossing)
Ability to operate with minimal supervision
Preferred
Experience in subsystem-level development
Exposure to D2D logic
Prior experience working directly with major hyperscaler silicon teams
Show more Show less
Position: RTL (Digital) Design Engineer
Work Type: REMOTE
Duration: 12 months (Possible Extension).
Description
We are seeking experienced RTL Design Engineers who can operate independently, collaborate closely with client leads, and commit to full project lifecycle ownership.
1. RTL Design Engineer
Key Responsibilities
Own micro-architecture definition from high-level functional specifications
Develop and implement RTL for complex digital blocks
Drive digital block control and IP integration
Participate in subsystem-level architecture alignment
Support design sign-off activities (CDC, RDC, lint, synthesis readiness)
Collaborate closely with DV for closure and debug
Required Qualifications
Strong expertise in RTL design (SystemVerilog/Verilog)
Experience defining micro-architecture independently
Solid understanding of memory controllers and digital subsystems
Experience with IP integration and block-level ownership
Familiarity with sign-off flows including:
CDC (Clock Domain Crossing)
RDC (Reset Domain Crossing)
Ability to operate with minimal supervision
Preferred
Experience in subsystem-level development
Exposure to D2D logic
Prior experience working directly with major hyperscaler silicon teams
Show more Show less