RTL Design Engineer

We’re looking for an experienced RTL Designer to develop and implement CPU datapath components, including:

• ALU, Load/Store units
• Vector & Matrix compute units
• Register files & instruction pipelines

Responsibilities:

• Implement microarchitecture in Verilog/SystemVerilog
• Collaborate with verification teams to ensure correctness
• Support front-end design flows: lint, CDC, synthesis

Requirements:

• 5+ years RTL design experience
• Strong Verilog/SystemVerilog skills
• CPU datapath and pipeline knowledge
• Familiarity with vector/matrix compute units

Preferred:

• RISC-V architecture experience

Pay Range: $70 - $80/hr on w2 (All inclusive)