R&D Engineering, Sr Staff Engineer

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years in the trenches of CMOS memory design and you know that a well-designed SRAM is not just about meeting spec, it is about understanding the tradeoffs between speed, power, and density at a level most engineers never reach. You are the person who sees a bit cell layout and immediately knows whether it will hold up under process variation, whether the read disturb margin is real or optimistic, and whether the timing path everyone is counting on will actually close.

You have built memories that shipped in production silicon. Not just simulated them, actually taped them out, brought them up in the lab, debugged the failures, and fixed them for the next spin. You know what it feels like when a design you spent months on comes back working, and you know what it takes to get there.

Schematic entry, SPICE simulation, layout planning, parasitic extraction, and design verification are not separate tasks for you, they are parts of a single flow you have internalized. You can switch from reviewing a circuit topology to writing a Perl script to automate layout checks without losing momentum. When a junior engineer brings you a setup time violation, you do not just tell them to resize a buffer, you walk them through why the violation exists and what it means for the architecture.

At Synopsys, you will design memory IP that powers some of the most advanced chips in the world, and you will work with a team that understands what it takes to get there.

What You'll Be Doing

Design and develop CMOS embedded memories including SP SRAM, DP SRAM, Register Files, and ROM across ultra high speed, ultra low power, and high density design portfolios
Own architecture definition and circuit implementation for memory compilers, making the critical tradeoffs that determine performance, area, and yield
Perform schematic entry, circuit simulation using SPICE-based tools, layout planning, and supervise physical layout teams through design closure
Develop and verify bit cells from initial topology exploration through full layout verification, including parasitic extraction and post-layout simulation
Interface directly with CAD teams to automate memory compiler flows and with frontend engineers to generate EDA models and enable full verification integration
Debug and resolve design issues across the full stack, from transistor-level failures to compiler automation bugs
Lead and mentor junior engineers and trainees on memory design methodology, circuit techniques, and verification best practices

The Impact You Will Have

Your memory IP will enable customers to build faster, lower-power chips across AI, mobile, automotive, and data center applications
The bit cells and architectures you develop will define the performance and power envelope for entire SoC platforms
Your compiler automation work will accelerate time-to-market for dozens of customer designs by enabling rapid memory generation and validation
The design techniques you establish will become the foundation for future memory generations across multiple process nodes
Your mentorship will build the next generation of memory designers who will carry forward the rigor and craft you bring to the work
The verification flows you help define will catch issues before tapeout, saving months of schedule and millions in respins
Your collaboration with CAD and frontend teams will close the loop between memory design and the tools that make it scalable

What You'll Need

Bachelor's or Master's degree in Electrical Engineering, Electronics, Telecommunications, or a related technical field
8+ years of hands-on CMOS memory design experience with production tapeout responsibility
Deep proficiency in memory circuit design, SPICE simulation, layout planning, parasitic extraction, and layout verification tools
Strong scripting capability in C-Shell and Perl; experience with C++ or JavaScript is a plus
Demonstrated experience developing bit cells and driving physical layout design through to verification closure
Experience interfacing with memory compiler automation flows and EDA model generation
Proven ability to lead technical projects and mentor junior engineers through complex design challenges

Who You Are

You can look at a memory timing diagram and immediately identify whether the access time claim is real or whether someone is hiding margin
When a layout comes back with LVS errors, you do not wait for the layout team to figure it out, you open the GDS yourself and find the short
You write documentation and design reviews that actually help people understand the decisions you made, not just what you built
You are comfortable presenting a circuit tradeoff to a senior architect and defending your approach with data, not intuition
You know when to push back on a spec that cannot be met and when to find a creative way to make it work
You stay current on memory design techniques and process technology trends because you care about building better circuits, not just finishing tasks

The Team You'll Be Part Of

Your recruiter will share more about the team structure and mission during the interview process.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
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