NS
R-10062783 Principal DFT Engineer
Accepting applicationsNXP Semiconductors · Austin, TX
Full-Time Mid_senior ATEATPGBISTDFTDfT
Posted
1 May
Category
Test
Experience
Mid_senior
Country
United States
DFT Engineer will join a team working on leading-edge projects in the Business Unit (BU) MCU & MPU Engineering & Design Enablement (MMEDE). MMEDE BU brings the technology and ecosystem relationships for next gen automotive Processing, Edge Processing & Radar Processing products.
Your Responsibilities:
Handling RTL Design for DFT related changes in both Subsystem level & Top level Designs.
Inserting of MBIST RTL for memories & Verifying them.
Analyzing Scan DRCs & fixing them in RTL.
Analyzing ATPG reports on coverage & devise mechanism to improve coverage & generating patterns for ATE.
Inserting of TAP, IOs, Test Pinmux using NXP DFT flows.
Power Aware RTL/ GLS simulation bring up & taking care of the regression suite for both Non-ATPG & ATPG simulations.
Bringing up Patterns on Wafer probe & on Final Test by working closely with Product & Test teams.
Your Profile:
DFT engineer with 7+ years of experience in DfT implementation and verification of scan architectures, JTAG, memory BIST, ATPG.
Self-driven, results-oriented with a positive outlook, and a clear focus on high quality deliverables.
Empathic communicator, able to see things from the other person's point of view.
Should be willing to take up new challenges in the project and be a team player.
The engineer should be well versed in Digital Design Concept, preferably having subject knowledge on Verilog/VHDL RTL coding.
The candidate should preferably have experience in any one of the following areas.
Scan insertion, JTAG, ATPG DRC and coverage analysis, Simulation debug with timing/SDF.
Able to debug and root cause problems in simulation failures.
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Your Responsibilities:
Handling RTL Design for DFT related changes in both Subsystem level & Top level Designs.
Inserting of MBIST RTL for memories & Verifying them.
Analyzing Scan DRCs & fixing them in RTL.
Analyzing ATPG reports on coverage & devise mechanism to improve coverage & generating patterns for ATE.
Inserting of TAP, IOs, Test Pinmux using NXP DFT flows.
Power Aware RTL/ GLS simulation bring up & taking care of the regression suite for both Non-ATPG & ATPG simulations.
Bringing up Patterns on Wafer probe & on Final Test by working closely with Product & Test teams.
Your Profile:
DFT engineer with 7+ years of experience in DfT implementation and verification of scan architectures, JTAG, memory BIST, ATPG.
Self-driven, results-oriented with a positive outlook, and a clear focus on high quality deliverables.
Empathic communicator, able to see things from the other person's point of view.
Should be willing to take up new challenges in the project and be a team player.
The engineer should be well versed in Digital Design Concept, preferably having subject knowledge on Verilog/VHDL RTL coding.
The candidate should preferably have experience in any one of the following areas.
Scan insertion, JTAG, ATPG DRC and coverage analysis, Simulation debug with timing/SDF.
Able to debug and root cause problems in simulation failures.
Show more Show less