NS
R-10061623 Senior Analog Validation/Characterization Engineer
Accepting applicationsNXP Semiconductors · San Jose, United States, North America
Full-Time Senior AnalogCadenceEthernetMixed-SignalPCIe
Posted
31 Mar
Category
Design
Experience
Senior
Country
United States
We are looking for a mid-level Mixed-Signal Engineer to join our Automotive Semiconductor division. This role bridges the gap between pre-silicon design and post-silicon reality. You will spend roughly 50% of your time developing behavioral models to speed up chip simulation and 50% of your time in the lab performing hands-on validation of high-speed transceiver silicon.
Key Responsibilities
- AMS Modeling: Create and maintain behavioral models (SystemVerilog/RNM, Verilog-A) for mixed-signal blocks to support full-chip functional verification.
- Hardware Validation: Perform bench-top characterization of high-speed transceivers (10G+) using standard lab equipment (Oscilloscopes, VNAs, BERTs).
- Python Scripting: Develop and optimize Python scripts to automate lab measurements, parse large datasets, and generate validation reports.
- Simulation: Run mixed-signal co-simulations (Cadence Virtuoso/Spectre) to verify connectivity and basic functionality of analog-digital interfaces.
- Cross-Functional Support: Collaborate with Design and Verification teams to debug silicon issues and correlate lab results with simulation data.
Skills & Qualifications
- Education: BSEE or MSEE with 3+ years of experience in IC modeling, design, or validation.
- Simulation Tools: Experience with Cadence Virtuoso, Spectre, or similar mixed-signal simulation environments.
- Modeling Languages: Proficiency in SystemVerilog (Real Number Modeling preferred) or Verilog-A.
- Test & Measurement: Hands-on experience with high-speed lab equipment for signal integrity and performance testing.
- Software/Scripting: Strong Python skills for automation (knowledge of libraries like NumPy, Matplotlib, or PyVISA is a plus).
Preferred Qualifications
- Familiarity with high-speed serial standards (e.g., SerDes, Ethernet, or PCIe).
- Experience working within a structured Product Development Process (PDP) in a large-scale semiconductor environment.
- Understanding of basic signal integrity concepts (jitter, eye diagrams, insertion loss).