MT
Processor Coherency Architect
Accepting applicationsMulya Technologies · Greater Bengaluru Area
Full-Time Mid_senior RTLateganrfsic
Posted
1d ago
Category
Design
Experience
Mid_senior
Country
India
Processor Coherency Architect
Fortune 100 Organization
Location: Bangalore
Your Role And Responsibilities
Develop on- and off-chip network microarchitectures for data and coherence transport that meet KPIs for next-generation SMP.
Work closely with Cache/Nest PD architect to specify structures/topologies that are logically and physically realizable by the development team by the target tape-out date.
Modify/develop cache coherence protocol that best supports coherence transport topology.
Develop improvements to L2 and LLC micro architectures that improve KPIs.
Work with core architects to develop improvements to L2-core interface and interactions that improves KPIs.
Required Technical And Professional Expertise
Minimum 15+ years of relevant experience with MS/PhD
Hands-on RTL level experience of architecting and delivering Coherency features in processor
Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP
Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations
Experience in working with Core architecture/ FW/ SW teams
Exposure to System architecture
Contact
Uday
Mulya Technologies
muday_bhaskar@yahoo.com
https://mulyatech.com/
Show more Show less
Fortune 100 Organization
Location: Bangalore
Your Role And Responsibilities
Develop on- and off-chip network microarchitectures for data and coherence transport that meet KPIs for next-generation SMP.
Work closely with Cache/Nest PD architect to specify structures/topologies that are logically and physically realizable by the development team by the target tape-out date.
Modify/develop cache coherence protocol that best supports coherence transport topology.
Develop improvements to L2 and LLC micro architectures that improve KPIs.
Work with core architects to develop improvements to L2-core interface and interactions that improves KPIs.
Required Technical And Professional Expertise
Minimum 15+ years of relevant experience with MS/PhD
Hands-on RTL level experience of architecting and delivering Coherency features in processor
Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP
Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations
Experience in working with Core architecture/ FW/ SW teams
Exposure to System architecture
Contact
Uday
Mulya Technologies
muday_bhaskar@yahoo.com
https://mulyatech.com/
Show more Show less