TC
Principal Verification Engineer – PCIe Gen5/Gen6
Accepting applicationsTechvy Corp · San Jose, CA
Contract Mid_senior ASICDFTFPGAPCIeRTL
Posted
19h ago
Category
Verification
Experience
Mid_senior
Country
United States
Principal Verification Engineer / Verification Lead – PCIe Gen5/Gen6
Location: San Jose, CA
Experience: 10+ Years
Job Type: Contract / Long-Term
Job Summary
We are seeking a highly experienced Principal Verification Engineer / Verification Lead to own end-to-end verification of a PCIe Gen5/Gen6 Controller and Subsystem.
The ideal candidate should have strong hands-on expertise in PCIe protocol verification, SystemVerilog, UVM, LTSSM, PIPE, PHY/SerDes integration, assertions, coverage closure, formal verification, and emulation.
Key Responsibilities
Own verification strategy and signoff for PCIe Gen5/Gen6 subsystems.
Develop verification plans covering Transaction, Data Link, and Physical Layers.
Architect reusable UVM environments at IP, subsystem, and SoC levels.
Verify LTSSM, PIPE, link training, equalization, recovery, speed changes, and lane-width changes.
Drive functional, code, assertion, and cross-coverage closure.
Verify Controller-to-PHY and SerDes integration.
Develop assertions, scoreboards, and protocol checks.
Support formal verification, emulation, and post-silicon debug.
Lead and mentor verification engineers.
Coordinate with Architecture, RTL, PHY, Firmware, DFT, and Validation teams.
Required Skills
10+ years of ASIC/SoC verification experience.
Strong PCIe Gen5/Gen6 verification experience.
Deep knowledge of PCIe Transaction, Data Link, and Physical Layers.
Strong SystemVerilog and UVM experience.
Strong knowledge of LTSSM, PIPE, PHY, and SerDes.
Experience with functional/code coverage and SystemVerilog Assertions.
Strong debugging and root-cause analysis skills.
Experience leading verification through tape-out.
Preferred Skills
SR-IOV
Formal Verification
Hardware Emulation
Post-Silicon Validation
SoC-level PCIe integration
FPGA prototyping
Key Skills: PCIe Gen5, PCIe Gen6, UVM, SystemVerilog, LTSSM, PIPE, PHY, SerDes, ASIC Verification, SoC Verification, SVA, Coverage, Formal Verification, Emulation.
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Location: San Jose, CA
Experience: 10+ Years
Job Type: Contract / Long-Term
Job Summary
We are seeking a highly experienced Principal Verification Engineer / Verification Lead to own end-to-end verification of a PCIe Gen5/Gen6 Controller and Subsystem.
The ideal candidate should have strong hands-on expertise in PCIe protocol verification, SystemVerilog, UVM, LTSSM, PIPE, PHY/SerDes integration, assertions, coverage closure, formal verification, and emulation.
Key Responsibilities
Own verification strategy and signoff for PCIe Gen5/Gen6 subsystems.
Develop verification plans covering Transaction, Data Link, and Physical Layers.
Architect reusable UVM environments at IP, subsystem, and SoC levels.
Verify LTSSM, PIPE, link training, equalization, recovery, speed changes, and lane-width changes.
Drive functional, code, assertion, and cross-coverage closure.
Verify Controller-to-PHY and SerDes integration.
Develop assertions, scoreboards, and protocol checks.
Support formal verification, emulation, and post-silicon debug.
Lead and mentor verification engineers.
Coordinate with Architecture, RTL, PHY, Firmware, DFT, and Validation teams.
Required Skills
10+ years of ASIC/SoC verification experience.
Strong PCIe Gen5/Gen6 verification experience.
Deep knowledge of PCIe Transaction, Data Link, and Physical Layers.
Strong SystemVerilog and UVM experience.
Strong knowledge of LTSSM, PIPE, PHY, and SerDes.
Experience with functional/code coverage and SystemVerilog Assertions.
Strong debugging and root-cause analysis skills.
Experience leading verification through tape-out.
Preferred Skills
SR-IOV
Formal Verification
Hardware Emulation
Post-Silicon Validation
SoC-level PCIe integration
FPGA prototyping
Key Skills: PCIe Gen5, PCIe Gen6, UVM, SystemVerilog, LTSSM, PIPE, PHY, SerDes, ASIC Verification, SoC Verification, SVA, Coverage, Formal Verification, Emulation.
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