NS
Principal Verification Engineer
Accepting applicationsNXP Semiconductors · Noida, Uttar Pradesh, India
Full-Time Mid_senior ARMC++DDRDFTEthernet
Estimated market salary
₹25-45 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
6d ago
Category
Verification
Experience
Mid_senior
Country
India
Principal Engineer - Digital IP Verification (G4)
Role Overview
We are seeking a highly motivated, technically strong, and execution-focused Individual Contributor to lead and deliver first-pass success for complex Digital IP and Subsystem verification programs. The role demands deep expertise in advanced verification methodologies, strong ownership mindset, and ability to collaborate across multi-disciplinary and global teams.
The individual will work closely with System Architecture, Design, DFT, Mixed Signal, and Validation teams across sites to address verification challenges spanning IP, Subsystem, and full SoC context, leveraging simulation, formal verification, hardware modeling, and pre/post silicon validation techniques.
Key Responsibilities
Lead end-to-end verification execution for complex IPs and Subsystems, ensuring high quality and first-pass silicon success
Evaluate, adopt, and deploy advanced and scalable verification methodologies to handle increasing design complexity
Own verification quality metrics across planning, execution, and closure phases
Drive ‘Zero Defect’ mindset through rigorous process adherence, coverage closure, and defect prevention strategies
Analyze existing verification flows and implement improvements to enhance efficiency, predictability, and quality
Contribute to and influence technical innovation within the team, including methodology evolution and automation
Collaborate effectively across local and global cross-functional teams including Design, DFT, Architecture, and Validation
Support pre-silicon and post-silicon validation activities where required
Technical Skills – Must Have
10–15 years of hands-on experience in IP or Subsystem verification for complex, multi-million gate designs
Strong expertise in HVLs such as SystemVerilog/UVM and proficiency in C/C++
Solid understanding of HDLs such as Verilog/VHDL
Experience with industry simulators such as VCS, NCSim, ModelSim, or Questa
Strong experience in testbench architecture, development, debugging, and verification closure
Proficiency in test planning, feature traceability, and functional/performance validation
Strong knowledge of assertions (SVA), functional coverage, and regression management
Solid understanding of microcontroller architectures (ARM cores) and interconnect protocols such as AHB, AXI, AMBA
Experience in memory subsystems including SRAM, Flash, DDR, and memory controllers
Technical Skills – Good To Have
Exposure to formal verification methodologies and tools
Experience with gate-level simulations and verification planning tools
Exposure to emulation and pre-silicon validation environments
Domain knowledge in automotive, graphics/vision accelerators, high-speed serial interfaces, or networking protocols such as Ethernet
Soft Skills & Leadership Expectations (Aligned To NXP Values)
**Customer Focus:** Demonstrates strong ownership towards delivering high-quality IPs aligned with customer expectations and product timelines
**Ownership & Accountability:** Takes complete responsibility for deliverables, proactively manages risks, and drives closure with minimal supervision
**Collaboration:** Works effectively with global and cross-functional teams, fostering open communication and knowledge sharing
**Innovation Mindset:** Actively contributes to continuous improvement, automation, and adoption of advanced verification practice
More information about NXP in India...
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Role Overview
We are seeking a highly motivated, technically strong, and execution-focused Individual Contributor to lead and deliver first-pass success for complex Digital IP and Subsystem verification programs. The role demands deep expertise in advanced verification methodologies, strong ownership mindset, and ability to collaborate across multi-disciplinary and global teams.
The individual will work closely with System Architecture, Design, DFT, Mixed Signal, and Validation teams across sites to address verification challenges spanning IP, Subsystem, and full SoC context, leveraging simulation, formal verification, hardware modeling, and pre/post silicon validation techniques.
Key Responsibilities
Lead end-to-end verification execution for complex IPs and Subsystems, ensuring high quality and first-pass silicon success
Evaluate, adopt, and deploy advanced and scalable verification methodologies to handle increasing design complexity
Own verification quality metrics across planning, execution, and closure phases
Drive ‘Zero Defect’ mindset through rigorous process adherence, coverage closure, and defect prevention strategies
Analyze existing verification flows and implement improvements to enhance efficiency, predictability, and quality
Contribute to and influence technical innovation within the team, including methodology evolution and automation
Collaborate effectively across local and global cross-functional teams including Design, DFT, Architecture, and Validation
Support pre-silicon and post-silicon validation activities where required
Technical Skills – Must Have
10–15 years of hands-on experience in IP or Subsystem verification for complex, multi-million gate designs
Strong expertise in HVLs such as SystemVerilog/UVM and proficiency in C/C++
Solid understanding of HDLs such as Verilog/VHDL
Experience with industry simulators such as VCS, NCSim, ModelSim, or Questa
Strong experience in testbench architecture, development, debugging, and verification closure
Proficiency in test planning, feature traceability, and functional/performance validation
Strong knowledge of assertions (SVA), functional coverage, and regression management
Solid understanding of microcontroller architectures (ARM cores) and interconnect protocols such as AHB, AXI, AMBA
Experience in memory subsystems including SRAM, Flash, DDR, and memory controllers
Technical Skills – Good To Have
Exposure to formal verification methodologies and tools
Experience with gate-level simulations and verification planning tools
Exposure to emulation and pre-silicon validation environments
Domain knowledge in automotive, graphics/vision accelerators, high-speed serial interfaces, or networking protocols such as Ethernet
Soft Skills & Leadership Expectations (Aligned To NXP Values)
**Customer Focus:** Demonstrates strong ownership towards delivering high-quality IPs aligned with customer expectations and product timelines
**Ownership & Accountability:** Takes complete responsibility for deliverables, proactively manages risks, and drives closure with minimal supervision
**Collaboration:** Works effectively with global and cross-functional teams, fostering open communication and knowledge sharing
**Innovation Mindset:** Actively contributes to continuous improvement, automation, and adoption of advanced verification practice
More information about NXP in India...
Show more Show less